How to implement basic read write operation in UFM onchip flash IP (Non-volatile memory)

[Shweta_sawant]

How to implement basic read write operation in UFM onchip flash IP (Non-volatile memory) in 10M16 FPGA in Quartus prime 17.0. 

https://community.intel.com/t5/Programmable-Devices/MAX10-UFM-Read-Operation/m-p/194877

I am facing the same error as her and need on urget basis. 

Best Regards,

Shweta Sawant

[Farabi]

Hello,

Please refer to design example here: https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset03/max10ufm-write-operation-ug.pdf

regards,

Farabi

[Shweta_sawant]

Hello,

We are facing the same problem as the link mentioned in the above question. 

https://community.intel.com/t5/Programmable-Devices/MAX10-UFM-Read-Operation/m-p/194877

We need it on urgent basis. Facing error in particularly read operation (read_valid signal not updating from onchip_flash IP).

Thankyou for your time.

Best Regards,

Shweta Sawant

[Shweta_sawant]

As per the document mentioned in the answer above, we developed the code as below. But, we are facing issue in tehe read operation.

Code

library ieee;

use ieee.numeric_std.all;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use ieee.std_logic_1164.all;

entity NVM_Read_write is 

port(

clock_20mhz_i :  in std_logic;

reset_ni :  in std_logic;

csr_readdata_i : in STD_LOGIC_VECTOR(31 DOWNTO 0);

waitrequest_i : in STD_LOGIC;

readvalid_i : in STD_LOGIC;

en_read_i : in STD_LOGIC;

en_write_i : in STD_LOGIC;

csr_addr_o : OUT STD_LOGIC;

csr_writedata_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

csr_write_o : OUT STD_LOGIC;

csr_read_o : OUT STD_LOGIC;

data_addr_o : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);

data_writedata_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

data_write_o : OUT STD_LOGIC;

data_read_o : OUT STD_LOGIC;

readvalid_counter_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

burstcount_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

end entity;

architecture arch of NVM_Read_write is

--type STATES is (STATE_RESET, STATE_DISABLE_WP, STATE_WR_DATA, STATE_WR_WAITREQ,  STATE_CHK_STATUS, STATE_EN_WP,

-- STATE_RD_DATA, STATE_RD_WAITREQ, STATE_RD_WAIT_RDVALID_HIGH, STATE_RD_WAIT_FINISH, STATE_INC_ADDR,

-- STATE_STOP_RD);

--signal STATE ,NEXT_STATE  : STATES;

SIGNAL STATE_s : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL NEXT_STATE_s : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL addr_counter_s : unsigned(31 DOWNTO 0);

SIGNAL data_addr_s : STD_LOGIC_VECTOR(12 DOWNTO 0);

SIGNAL readvalid_counter_s : STD_LOGIC_VECTOR(3 DOWNTO 0);

CONSTANT STATE_RESET_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; -- Reset

CONSTANT STATE_DISABLE_WP_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; -- Disable write protection

CONSTANT STATE_WR_DATA_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; -- write data up to address#256

CONSTANT STATE_WR_WAITREQ_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; -- increase the address counter only when waitrequest goes low

CONSTANT STATE_CHK_STATUS_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; -- check status register to confirm write is successful

CONSTANT STATE_EN_WP_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; -- enable back write protection

CONSTANT STATE_RD_DATA_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110"; -- read data

CONSTANT STATE_RD_WAITREQ_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111"; -- if waitrequest goes high, check readvalid signal

CONSTANT STATE_RD_WAIT_RDVALID_HIGH_c: STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000"; -- if readvalid signal goes high, check readvalid counter

CONSTANT STATE_RD_WAIT_FINISH_c: STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001"; -- check if readvalid counter reached 8

CONSTANT STATE_INC_ADDR_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010"; -- increase the addrress by 8 since the burstcount is set to 8 for burst read 

CONSTANT STATE_STOP_RD_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011"; -- stop reading if addrress reach 256

begin

data_addr_o<= data_addr_s;

readvalid_counter_o<= readvalid_counter_s;

process (reset_ni, clock_20mhz_i) is  

begin

if reset_ni='0' then 

STATE_s <= STATE_RESET_c;

elsif rising_edge(clock_20mhz_i) then

STATE_s <= NEXT_STATE_s;

end if;

end process;

process (reset_ni, clock_20mhz_i) is  

begin

if reset_ni='0' then 

data_addr_s <= (others =>'0');

addr_counter_s <= (others =>'0');

csr_addr_o <= '0';

csr_write_o <= '0';

csr_writedata_o <= x"FFFFFFFF";

burstcount_o <= "0000";

elsif rising_edge(clock_20mhz_i) then

case STATE_s is

When STATE_RESET_c =>

data_addr_s <= (others =>'0');

addr_counter_s  <= (others =>'0');

csr_addr_o <= '0';

csr_write_o <= '0';

csr_writedata_o <= x"FFFFFFFF";

burstcount_o <= "0000";

data_write_o <= '0';

data_read_o <= '0';

When STATE_DISABLE_WP_c =>

csr_addr_o <= '1';

csr_write_o <= '1';

csr_writedata_o <= x"FC7FFFFF";

burstcount_o <= "0001";

When STATE_WR_DATA_c =>

csr_addr_o      <= '0';

csr_write_o      <= '0';

csr_writedata_o  <= x"FFFFFFFF";

data_addr_s   <= std_logic_vector(unsigned(addr_counter_s(12 downto 0)));

data_write_o   <= '1';

data_writedata_o <= std_logic_vector(unsigned(addr_counter_s));

When STATE_WR_WAITREQ_c =>

if waitrequest_i ='0' then

addr_counter_s <= addr_counter_s + 1;

data_write_o   <= '0';

end if;

When STATE_CHK_STATUS_c =>

data_write_o <= '0';

csr_addr_o   <= '0';

csr_read_o   <= '1';

When STATE_EN_WP_c =>

csr_addr_o    <= '1';

csr_write_o   <= '1';

csr_writedata_o <= x"FFFFFFFF";

data_addr_s   <= "0000000000000";

When STATE_RD_DATA_c  =>

data_read_o  <= '1';

burstcount_o <= "1000";

When STATE_RD_WAITREQ_c  =>

When STATE_RD_WAIT_RDVALID_HIGH_c  =>

data_read_o <= '0';

When STATE_RD_WAIT_FINISH_c  =>

When STATE_INC_ADDR_c  =>

data_addr_s <= data_addr_s + "0000000001000";

When STATE_STOP_RD_c  =>

data_read_o <= '0';

data_addr_s <= (others => '0');

when others =>

NULL;

end case;

end if;

end process;

process (en_read_i,en_write_i) is  

begin

if (en_read_i='0') and  (en_write_i='0') then  

NEXT_STATE_s <= STATE_RESET_c;

else

case STATE_s is

When STATE_RESET_c =>

if en_write_i ='1' then 

NEXT_STATE_s <= STATE_DISABLE_WP_c;

else

if en_read_i='1' then

NEXT_STATE_s <= STATE_RD_DATA_c;

else

NEXT_STATE_s <= STATE_RESET_c;

end if;

end if;

When STATE_DISABLE_WP_c =>

NEXT_STATE_s <= STATE_WR_DATA_c ;

When STATE_WR_DATA_c =>

NEXT_STATE_s <= STATE_WR_WAITREQ_c;

When STATE_WR_WAITREQ_c =>

if waitrequest_i = '0' then

if addr_counter_s < x"00000100" then

NEXT_STATE_s <= STATE_WR_DATA_c;

else

NEXT_STATE_s <= STATE_CHK_STATUS_c;

end if;

else

NEXT_STATE_s <= STATE_WR_WAITREQ_c;

end if;

When STATE_CHK_STATUS_c =>

NEXT_STATE_s <= STATE_EN_WP_c;

When STATE_EN_WP_c => 

if csr_readdata_i(3) = '1' then

NEXT_STATE_s <= STATE_RESET_c;

else 

NEXT_STATE_s <= STATE_EN_WP_c;

end if;

When STATE_RD_DATA_c =>

if data_addr_s <= "0000100000000" then

NEXT_STATE_s <= STATE_RD_WAITREQ_c;

else

NEXT_STATE_s <= STATE_STOP_RD_c;

end if;

When STATE_RD_WAITREQ_c =>

if waitrequest_i = '1' then

NEXT_STATE_s <= STATE_RD_WAIT_RDVALID_HIGH_c;

else

NEXT_STATE_s <= STATE_RD_WAITREQ_c;

end if;

When STATE_RD_WAIT_RDVALID_HIGH_c =>

if readvalid_i = '1' then

NEXT_STATE_s <= STATE_RD_WAIT_FINISH_c;

else

NEXT_STATE_s <= STATE_RD_WAIT_RDVALID_HIGH_c;

end if;

When STATE_RD_WAIT_FINISH_c =>

if readvalid_counter_s = "1000" then

NEXT_STATE_s <= STATE_INC_ADDR_c;

else

NEXT_STATE_s <= STATE_RD_WAIT_FINISH_c;

end if;

When STATE_INC_ADDR_c =>

NEXT_STATE_s <= STATE_RD_DATA_c;

When STATE_STOP_RD_c =>

NEXT_STATE_s <= STATE_STOP_RD_c;

when others =>

NULL;

end case;

end if;

end process;

process (clock_20mhz_i ) is

begin 

if rising_edge(clock_20mhz_i ) then

if en_read_i ='0' then

readvalid_counter_s <= "0000";

elsif en_read_i ='1' then

if readvalid_i = '1' then

readvalid_counter_s <= readvalid_counter_s + "0001";

elsif readvalid_counter_s = "1000" then ---hex8

readvalid_counter_s <= "0000";

end if;

end if;

end if;

end process;

end architecture;

[Fakhrul]

Hi Shweta_sawant,

Could you specify the error encountered? If available, please provide any error codes or numbers, and consider sharing a screenshot for better assistance. Kindly refer to the instructions in sub-topic 4.2.6, "UFM Read Operation," on page 16 of the Intel® MAX® 10 User Flash Memory User Guide

Regards,

Fakhrul

[Shweta_sawant]

selected signal are not available from ON chip flash IP. 

[Fakhrul]

Hi Shweta_sawant,

Could you send us with full design as we may need to try to replicate it on our side to further debug the issue.

Regards,

Fakhrul

[Shweta_sawant]

Hello,

We are not able to get avmm_data_readvalid_i and avmm_data_waitrequest_i as 1 even after the avmm_data_readata is being updated by the memory. 

[Shweta_sawant]

This is the project file 

[Fakhrul]

Hi Shweta_sawant,

Just would like to check whether have you go to Tools -> In-System Sources and Probes Editor and toggle the Index S[0] to start?

Regards,

Fakhrul

[Fakhrul]

Since we haven't heard back from you about our previous message, we'll now move this discussion to community support. Feel free to start a new thread for any new questions or issues you have – our Intel experts will be there to help. But if you don't have more questions, the community users can still assist you here. Thanks for your understanding.