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Beginner
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How to include user vhdl defined package in ModelSim-Altera RTL Simulation?

I can compile my design in Quartus Prime Lite Edition.

I can run the RTL Simulation using ModelSi -Altera well.

The problem happens when I included a package vhdl file as follows:

1- I created user_pkg.vhd file and placed it in Sources folder, the file has a package called: example_package

2- The Testbench file imports example package as follows:

library work;

use work.example_package.all;

3- Quartus compiles successfully

4- Then ModelSim RTL Simulation crashes at:

 

# ** Error: (vcom-11) Could not find work.example_package

# ** Error (suppressible): Cannot find expanded name "work.example_package".

Unknown expanded name.

 

 

 -------------------------

 

 

I solved it by manually adding:

vcom -93 -work work {C:/intelFPGA_lite/Projects/....../user_pkg.vhd}

to the run_msim_rtl_verilog.do file

 

how to do that automatically in Quartus so that I don't have to do it everytime I launch rtl_sim?

 

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3 Replies
62 Views

Try adding the user_pkg.vhd file in your projects and see if it helps.

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Beginner
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Thank you Richard, however it didn't help,

I actually solved it by adding :

vcom -93 -work work {C:/intelFPGA_lite/Projects/......./Sources/user_pkg.vhd}

to:

C:/intelFPGA_lite/Projects/......./simulation/modelsim/[project_name]_run_msim_rtl_verilog.do

to include it in the list of compiled files

 

The problem is I have to do this manually, I hope there was a way to configure it automatically from Quartus.

 

 

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62 Views

Hi Ahmed,

 

Have you tried using nativelink feature in your simulation?

Reference:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/desig...

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