How to migrate Xilinx Primitives to Intel Quartus Design?

[Shenoy]

I have LUT1, LUT4, SRL16, FD (D-Flop) primitives used in Xilinx based module by including

library unisim;

use unisim.vcomponents.all; in the module. Now I want migrate my design for Intel FPGA. How to do this?

[ak6dn]

Simplest way is to write verilog/vhdl functional models as modules for the Xilinx primitives you use. Then just include those in your source and compile with Altera tools.

In some cases (like DFF) you might find more or less exact replacements using Altera primitives (probably with port renaming) but this is a level of optimization probably not necessary.

[GuaBin_N_Intel]

Another way is to find any equivalent function or primitive block from the HDL coding template where located in any .v or .vhdl files > right-click Insert Template > VHDL/Verilog HDL > Altera Primitive .

[Shenoy]

I written some similar RTLs for primitives used and included them in quartus project.