I have LUT1, LUT4, SRL16, FD (D-Flop) primitives used in Xilinx based module by including
use unisim.vcomponents.all; in the module. Now I want migrate my design for Intel FPGA. How to do this?
Simplest way is to write verilog/vhdl functional models as modules for the Xilinx primitives you use. Then just include those in your source and compile with Altera tools.
In some cases (like DFF) you might find more or less exact replacements using Altera primitives (probably with port renaming) but this is a level of optimization probably not necessary.