How to observe Verilogcode execution sequence of Statements in ModelSim 11.1d

[Altera_Forum]

Hi All, 

I am using ModelSim 11.1d to simulate my Verilog code and I am trying to understand and watch the sequence of statements executed. How do I see the sequence of events in the simulator? Which commands are needed ? Thanks, Charlie

[Altera_Forum]

--- Quote Start ---  Hi All, I am using ModelSim 11.1d to simulate my Verilog code and I am trying to understand and watch the sequence of statements executed. How do I see the sequence of events in the simulator? Which commands are needed ? Thanks, Charlie  --- Quote End ---    verilog or vhdl are not software and sequence of execution does not apply. The parser does go through all statements and may give you syntax errors or other errors but once code is compiled into netlist it is no longer relevant. The netlist is description of generated circuit. Compiler does not build sequentially as it goes through code but looks at all picture then creates netlist.

[Altera_Forum]

Hi Kaz, 

The tutorial I am following was trying to explain the timing sequence of initial and fork blocks and adding delays . The tutorial says: "To give you a step-by-step description of what happens, Verilog has a trace mode. The example shows the results of running the simulation with the trace mode." I am trying to generate the the timing output as listed in the last section of this email but I have been unsuccessful so for.... Sorry for the lengthy reply but I thought it was necessary. ----------------------------------- Tutorial Example Verilog code: module initial_two_begin; initial  begin # 1 $display("Statement 1");  $display("Statement 2"); # 2 $display("Statement 3");  end initial  begin  $display("Block 2 Statement 1"); # 2 $display("Block 2 Statement 2"); # 2 $display("Block 2 Statement 3");  end endmodule -------------------------------------------- The output is: Block 2 Statement 1 Statement 1 Statement 2 Block 2 Statement 2 Statement 3 Block 2 Statement 3 -------------------------- "Both "initial" blocks start at the same time. However, the first initial block encounters a delay, so the first event that occurs is the $display in the second block. To give you a step-by-step description of what happens, Verilog has a trace mode. Example shows the results of running the simulation with the trace mode." And here is portion of the result that I want to generate and have not been successful: ------------------------------- L3 "i2b.v" (i2b): INITIAL  L4 "i2b.v" (i2b): BEGIN  L4 "i2b.v" (i2b):# 1  L10 "i2b.v" (i2b): INITIAL  L11 "i2b.v" (i2b): BEGIN  L12 "i2b.v" (i2b): $display ("Block 2 Statement 1")  Block 2 Statement 1  L11 "i2b.v" (i2b):# 2  SIMULATION TIME IS 1  L4 "i2b.v" (i2b):# 1 >>> CONTINUE  L5 "i2b.v" (i2b): $display ("Statement 1")  Statement 1  L6 "i2b.v" (i2b): $display ("Statement 2")  Statement 2  L4 "i2b.v" (i2b):# 2  SIMULATION TIME IS 2  L11 "i2b.v" (12b):# 2 >>> CONTINUE ....... ......

[Altera_Forum]

I'm not sure I understand the issue you have. The three sections you posted are all consistent with each other: the example code, output and trace (what you've posted of the trace anyway). 

 Yes, the two initial statements will start together.  Block 2 has no delay before the display. So, it's displayed first. There is then a delay of# 2 before that initial block does anything else.  In the mean time, block 1's# 1 completes. So, 'Statement 1' & 2 are displayed. Although these statements occur 'simultaneously' they are displayed sequentially as there is no other way to display simultaneous events. Block 1's# 2 now starts...  ...which allows block 2's statement 2 to occur... and so on.  So, as already stated, the code, output and trace you've posted all do as I'd expect.  Regards, Alex

[Altera_Forum]

Hi Alex, 

What commands/statements do I need in order to generate the trace in ModelSim 11.1d, for the Verilog code? I have been unable to generate the trace. (Note: The posted trace is not mine, but from a tutorial) Regards, Charlie

[Altera_Forum]

That trace looks like it may be from Verilog-XL; an interpretive simulator that no longer exists. 

 In Modelsim, you can use the step and see commands to get similar output.  For longer traces, you may want to use a Tcl script.   proc linetrace1000 {} { for { set n 0} { $n < 1000 } {incr n} { step; see 0 }}

[Altera_Forum]

Thank you dave_59, I typed the line of code you provided and after reading about Tcl and its keywords in Modelsim Help menu, I realized I needed to type the proc name linetrac1000 to invoke the command then I watched the generated trace. I was stuck on this problem for a long time and I really appreciate your help resolving it. 

Best Regards, Charlie