Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to preserve P&R resultes and resued in another same project ?

Altera_Forum
Honored Contributor II
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Hi all friends,  

 

I have a project with unstable timing results. So I want to preserve a good timing result try and make it resued for futrue compilation. I make several partitions and export as POST-FIT netlist. Then they are imported to another same project. Does it mean that I can preserve these partitions P&R results and achieve the same timing results? Or there might be some constrains to make a complete preservation? :confused: 

Thanks a lot !
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Altera_Forum
Honored Contributor II
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When you import the partitions with P&R locked, the timing will be preserved (with a caveat) and any timing constraints should have no effect on the already placed and routed part of the design. The caveat on preserving the timing is that there can be slight timing differences depending on internal crosstalk from other logic in the device. These are usually in the order of less than 50 ps however.

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Altera_Forum
Honored Contributor II
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Thanks a lot! :)

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