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15546 Discussions

How to print Counter output in NIOS console ?

SS5
Novice
1,097 Views

Hello,

I have followed this topic Simulating Designs with Lower-Level Qsys Systems as example design.

 

But i want to read the counter incremented data in NIOS console. Please suggest me , how .

 

Shall i add PIO- 8-bit output in SOPC builder and whether it can be possible to read ? ?

 

0 Kudos
10 Replies
a_x_h_75
New Contributor III
244 Views

Yes - you can add another PIO - configured as an input - and connect your 'count'' output signal to it. You can then use an 'IORD' instruction to read the value of the port.

 

Cheers,

Alex

SS5
Novice
244 Views

Thanks for your response.

 

Please check my NIOS_code. Without FOR LOOP, how should i run the counter module.

#include "sys/alt_stdio.h" #include "alt_types.h" #include<io.h> #include<system.h> #include<stdio.h>   int main() { int result,i; IOWR(ENABLE_BASE, 0, 0x0); // Enable the counter alt_printf("Hello from Nios II!\n"); // Send Hello World to the JTAG UART usleep(100); for (i=0;i<10000;i++)   { result=IORD(COUNTER_OUT_BASE, 0); printf("%d\n",(result+i)); } // IOWR(ENABLE_BASE, 0, 0x1); return 0; }

 

SS5
Novice
244 Views

I am not sure whether my design flow is right ?

Please suggest me

module counter ///SUB   ( input clk, enable, rst_n, output reg[7:0] count );   always @ (posedge clk or negedge rst_n) begin if (~rst_n) count <= 0; else if (enable == 1'b1) count <= count + 1; end   endmodule module Counter_Top_Level_design ///TOP ( input clk, input rst_n, output [7:0] out );   wire counter_enable;   counter counter_inst ( .clk ( clk ), .rst_n ( rst_n ), .enable ( counter_enable ), .count ( out ) );   // For simulation, use this instantiation: NIOS_SYSTEM niosii_system_inst ( .clk_clk ( clk ), // clk.clk .reset_reset_n ( rst_n ), // reset.reset_n .enable_external_connection_export ( counter_enable ), // output_pio.export .cout_export ( count ) ); endmodule

NIOS

int result,i; IOWR(ENABLE_BASE, 0, 0x0); // Enable the counter alt_printf("Hello from Nios II!\n"); // Send Hello World to the JTAG UART usleep(100); for (i=0;i<10000;i++) { result=IORD(COUNTER_OUT_BASE, 0); printf("%d\n",(result+i)); }

 

 

a_x_h_75
New Contributor III
244 Views

Your connection to 'cout_export' should be 'out', not count which doesn't exist in 'Counter_Top_Level_design' (only in 'counter').

 

As for the Nios code - it looks fine.

 

>>""Without FOR LOOP, how should i run the counter module.""

 

Without knowing what you're trying to do I don't know what to suggest.

 

Cheers,

Alex

SS5
Novice
244 Views

Sorry :)

As per your instruction i have modified the code.

How to justify counter design is working or not ?

I have attached the screenshot in that only FOR loop is increaming ,

Nios.JPG

SS5
Novice
244 Views

Design FLOW :From Quartus, i want to read the counter data in NIOS through QSYS.

 

  1. Giving Enable signal as PIO output -1-bit
  2. Reading Counter Data as PIO INPUT -8 bit

Please go through from the starting .

 

a_x_h_75
New Contributor III
244 Views

>> IOWR(ENABLE_BASE, 0, 0x0);

 

This is DISABLING the counter, not enabling it. Your verilog code has an active LOW reset in the counter module.

 

Cheers,

Alex

SS5
Novice
244 Views

Yes, you are right. Thanks

 

But , In Nios counter data is printing slow. Any suggestion, How to sort it out. Please view the attached screenshot.

 

a_x_h_75
New Contributor III
244 Views

Are you expecting too much from printf? It's a VERY slow function and I can quite imagine 1000's of clock cycles happening between each of your IORD instructions.

 

Cheers,

Alex

SS5
Novice
244 Views

I am stuck in this task for Past one week. Please tell me the Solution how to sort it out., as i am New to Altera Quartus.

 

Any Memories blaock will work it out like FIFO, SDRAM etc.

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