Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15317 Discussions

How to properly connect signals in schematic project for QUARTUS II

MBell6
Beginner
930 Views

Hi,

I'm forced to use schematic approach for a project (instead of VHDL). My problem is the following: I have two buses, for istance BUS_A[3..0] and BUS_B[2..0], I would like to connect BUS_A[3] signal with BUS_B[2] signal. How can I realize such an assignment?

Thanks everybody

 

0 Kudos
1 Reply
Vicky1
Employee
51 Views

Hi,

In this case, bus need to be split like (BUS_A[3..1],BUS_A[0]) or (BUS_A[3],BUS_A[2],BUS_A[1],BUS_A[0])

Refer the below old thread & screenshot for your reference,

https://forums.intel.com/s/question/0D50P00003yyG8bSAE/how-to-extract-1bit-from-a-bus-in-a-block-dia...

bdf.JPG

please provide screenshot of your bdf file for better support.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

 

Reply