Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15558 Discussions

How to raise error from vhdl code in Quartus?

LKrup
Novice
222 Views

Hi, is there any way to raise error in quartus synthesis from vhdl code?

Assert or report error/failure not work in Quartus synthesis.

0 Kudos
1 Reply
sstrell
Honored Contributor III
159 Views

There's no concept of error reporting when you're synthesizing into hardware. Where should the error be reported and how (unless you create actually hardware to handle this)? HDLs were initially designed for simulation, not synthesis, so they have a lot of extra features that work in a simulation tool but make no sense or can't be implemented in hardware.

 

#iwork4intel

Reply