Hi, is there any way to raise error in quartus synthesis from vhdl code?
Assert or report error/failure not work in Quartus synthesis.
There's no concept of error reporting when you're synthesizing into hardware. Where should the error be reported and how (unless you create actually hardware to handle this)? HDLs were initially designed for simulation, not synthesis, so they have a lot of extra features that work in a simulation tool but make no sense or can't be implemented in hardware.