I have a FPGA system which include both DDR4 IP and USB3 controller. The Quartus prime 18.1 build 222 has inserted lots of Unused_RX_Clock_Workaround_PMR_CDR_PLL during place&route:
Location : HSSIPMACDRPLL_1C0
datarate ; 1.0 ms
output_clock_frequency ; 2.9 ms
reference_clock_frequency ; 100us
vco_freq ; 8.0ms
How to get rid of these UNUSED_WORKAROUND PLLs?
- FPGA Design Tools
Based on my understanding, you are referring to “Transmitter PLL” in the GXB Report.
To get rid of these unused PLLs you need to turn OFF the “ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON” in your .QSF as below and re-compile your project.
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND OFF
set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND OFF -to <pin name>
After compilation, you should able to see the Total PLLs number decrease and there is no Transmitter PLL generated in your Fitter report.
I sincerely hope this helps.
Many thanks for your help!
However, I have tried to add the command "set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND OFF" only in the QSF firstly.
It didn't work and those "Transmitter PLL" are still there.
For another command "set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND OFF -to <pin name>",
I don't know which pin name should be assigned here ? How to find the related "Pin Name" from the output log file ?
Would you kindly give me some guide ?
I have tried the command in my DDR4 example design and its work. The Fitter successfully generated without any “Transmitter PLLs”. I attached together my .QAR example design for your reference.
You can see in my .QSF (line 190 and 191) which I turn OFF the “ENABLE_UNUSED_RX_CLOCK_WORKAROUND”. Please also note that you need to add both of the command in your .QSF before compilation. For the <pin name>, its actually depend on your design. I recommend you to try the pin that fit into your design.
Hope this helps.