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Hi
I am trying to clear timing violations of my design. But after breaking the critical paths, I need to wait for minimum of 8 hours to get the next synthesis/timing results. Is there any way to clear the timing violations by speeding the synthesis flow? Any inputs would be helpful.
Thanks and regards
Shreyas
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What device that you were using? Some of the design have rapid recompile option. If you do not have this option, you will have to wait for it.
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You can make use of the concurrent compilation feature. Meaning, you can start analyzing timing at earlier stages (Plan/Place) while the design continues to compile and make some early judgement from there.
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You any further question?
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No, that helped, thanks!
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