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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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15384 Discussions

How to resolve timing violations quickly

shreyas
Beginner
405 Views

Hi

 

I am trying to clear timing violations of my design. But after breaking the critical paths, I need to wait for minimum of 8 hours to get the next synthesis/timing results. Is there any way to clear the timing violations by speeding the synthesis flow? Any inputs would be helpful.

 

Thanks and regards

Shreyas

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4 Replies
Kenny_Tan
Moderator
224 Views

What device that you were using? Some of the design have rapid recompile option. If you do not have this option, you will have to wait for it.

skyjuice
Employee
224 Views

You can make use of the concurrent compilation feature. Meaning, you can start analyzing timing at earlier stages (Plan/Place) while the design continues to compile and make some early judgement from there.

Kenny_Tan
Moderator
224 Views

You any further question?

shreyas
Beginner
224 Views

No, that helped, thanks!

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