How to select between the BRAM and Distributed Logic implementation?

[ldm_as]

Hi All,

The Quartus has the RTL code Templates for implementation of the Simple and True Dual Port RAMs.

But, how could I guide the tool which implementation of the BRAM I would prefer - Distributed Logic or BRAM implementation?

Is there a direct instance of a BRAM, which could be used in RTL code?

Thank you!

[ak6dn]

Lookup the ALTSYNCRAM IP core in the Altera Megawizard. You can parameterize this memory block to use (for example) M9K memory blocks, or force it to use LC (logic cells), etc.

[Kenny_Tan]

You can use ram style attribute, this attribute exist in the template as well

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_ram.htm

[ldm_as]

I'm using the Quartus-II. From my understanding, the Altera Megawizard is not available since v14.x.

I tried to look in the Platform Designer (aka Qsys), there are RAM IPs there, but they do not have any BRAM/LC selection attributes. The same for the RAM HDL Templates.

How do you use the Altera Megawizard for Quartus-II ?

[ak6dn]

Ok, sorry, I use two different versions of Quartus (13.0sp1 for older devices, 16.0 for new devices).

So in 16.0 or later, go to TOOLS menu, and select IP CATALOGS.

Over on the right hand window, then select LIBRARY, BASIC FUNCTIONS, then ON CHIP MEMORY.

Choose 1 or 2 port RAM (or ROM, whatever you want). Double click on it and it should throw up a dialog box to setup a new instance and then allow you to configure it.

If you have already chosen your device, then it will show on the first configuration dialog items to select implementation type (ie, M9K block ram vs LC logic cell).

Configure away, and save the black box and the instantiation template file, which you can then copy the contents to your design.

[Kenny_Tan]

The other way to get the template is

Open a new .v files, right click -> insert template.

from there, browse to attribute directory

Thanks

[ldm_as]

ak6dh, I tried as you described it and it works, thanks!

KennyT_Intel, the RAM Template doesn't include any attributes related to the RAM implementation. What did you mean when you noted "browse to attribute directory"? The "Insert Template" window doesn't have an attribute directory/section... I'm about Quartus v19.2

[Kenny_Tan]

Here is the full steps:

1) open the .v files

2) rigth click on the .v files -> insert template

3) Verilog HDL -> Synthesis attribute -> ramstyle attribute

You will see the example there, u can try use bram to see if it works.

Let me know if this helps?

[Kenny_Tan]

Any update?