Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15553 Discussions

How to set constrain rules when there are negative slacks on hold time analysis

NZhan1
Partner
327 Views

In Timequest, we can get hold time analysis. What could we do, when there were negative slacks on hold time analysis.

0 Kudos
2 Replies
skyjuice
Employee
186 Views

We need to understand the reason behind hold failure. In most cases, Quartus will add additional routing delay to satisfy hold requirements unless these problematic paths are not realistic to begin with.

Are these cross-clock transfers? Do they have huge clock skew?

Kenny_Tan
Moderator
186 Views

Any update?

Reply