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hoi
Beginner
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How to simulate Cyclone V HPS sdram interface with Quartus 18.1

Hi Intel

 

Is there any tutorial about simulation of HPS sdram interface with Quartus 18.1? I generated the simulation files with Platform Designer, but the waveform seems weird. The wait request signal was high all the time.

 

Thanks

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Hi,

You can use the GHRD that is available in your installation files, and recompile:

~intelFPGA/18.1/embedded/examples/hardware/cv_soc_devkit_ghrd

 

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