How to simulate IP using Modelsim.

[TPH_zenith]

I am new to Quartus Prime Pro 20.1. The last time I used Quartus it was Quartus II 13.1. I generated a dual port ram core and I want to simulate it in Modelsim PE. I generated libraries for modelsim using the EDA simulation library compiler. The last time I did this I loaded a VHDL file generated by the megawizard into modelsim along with my VHDL file containing the dual port ram. When I do this now I get an error in modelsim telling me it cannot find the library ram_2port_2010. It appears the dual port ram VHDL file points to this library. What should I do to fix this? I am not a tcl script user.

[RichardTanSY_Intel]

For Quartus Prime Pro Modelsim Simulation, you may checkout the User Guide in the link below:
A design example is attached in the user guide as a tutorial for beginner. Search Quartus_Pro_PLL_RAM.zip.

https://www.intel.com/content/www/us/en/programmable/documentation/yur1496247032051.html

Here's are some brief steps: 

1. After you finished the compilation for your project, go to Tools > Generate Simulator Setup Script for IP.  A file will be generated at your <project directory>/../mentor/msim_setup.tcl

2. Create a new Modelsim project at your project directory.  

3. In the Modelsim transcript window, source the msim_setup.tcl file which was generated in Step 1. Then insert the next two commands to compile the library and ip simulation files.

Modelsim> source msim_setup.tcl
Modelsim> dev_com
Modelsim> com

4. Next, compile your design and testbench files in Modelsim. 

Modelsim> vlog -vlog01compat -work work design.v
Modelsim> vlog -vlog01compat -work work testbench.v

5. Lastly, specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. (The top-level entity of your simulation is often a testbench that instantiates your design) Elaborate the design and run the simulation. 

Modelsim> set TOP_LEVEL_NAME testbench 
Modelsim> elab
Modelsim> add wave *
Modelsim> view structure
Modelsim> view signals
Modelsim> run -all

All of this can be done easier and faster if you pre-write a mentor_example.do script template as shown in the user guide Figure 4. Good for repetitive. 

Though, you might need to modify the TOP_LEVEL_NAME and compilation step appropriately as you continue with different design. 

[RichardTanSY_Intel]

Hi, 

We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

[David32]

I would like to extend the original question to the case where my design uses multiple IP cores.

For a single IP the answer above works fine, however, how to handle the multiple core case?

Thanks

David

[RichardTanSY_Intel]

You can use the scripted simulation flow or nativelink simulation flow (Quartus Standard version only). Both should works. 

For further information, you may checkout the supported simulation flow for Quartus Pro. 

https://www.intel.com/content/www/us/en/docs/programmable/683870/22-4/supported-simulation-flows.html

Best Regards,

Richard Tan

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