How to simulation PLL in ModelSim-Altera ?

Altera_Forum · ‎08-09-2016

Hi, All.

I'm trying to run simulate PLL for Cyclone(I) unsuccessful. What I use? QuartusII v11sp1 (last version that support CycloneI), ModelSim Altera Starter edition 6.6.

Assignment - Settings - Simulation: I guess this field should be Verilog HDL and 1 ps, the same as "PLL simulation example". But I'd prefer VHDL, because I know it little better (but I'm newbie still). Possible, it don't need for read or write.

Tools - Run EDA Simulation Tools -{RTL | Gate Level} which is better? Example works with both.

Example uses tcl script. What? Should I learn one more language? Oh, no! Not again!...

When I'm trying simulate my Sch top level project, "Gate Level" mode misses library when I press "Start simulation" (on initialize Modelsim all ok). When I'm trying simulate RTL, ModelSim cretes 3 different library: "work" - with VHDL comonents, "gate_work" and "rtl_work" with top-level blocks.

What should I do that it start works correctly? Or what I need show for more correct question?

...
wave modify -driver freeze -pattern clock -initialvalue 0 -period 200ns -dutycycle 50 -starttime 0ns -endtime 10000ns NewSig:/Block1/S_IN#  Block1
wave modify -driver freeze -pattern constant -value 1 -starttime 0ns -endtime 10000ns NewSig:/Block1/D_RDn#  Block1
wave export -file testbench -starttime 0 -endtime 10000 -format vlog -designunit Block1
vsim -voptargs=+acc gate_work.Block1#  vsim -voptargs=+acc gate_work.Block1 #  Loading gate_work.Block1#  ** Error: (vsim-3033) asnnet.vo(288): Instantiation of 'cyclone_lcell' failed. The design unit was not found.#          Region: /Block1#          Searched libraries:#              E:\Altera\PRJ\asnnet\simulation\modelsim\gate_work#  ** Error: (vsim-3033) asnnet.vo(325): Instantiation of 'cyclone_lcell' failed. The design unit was not found.#          Region: /Block1#          Searched libraries:#              E:\Altera\PRJ\asnnet\simulation\modelsim\gate_work
...

Altera_Forum · ‎08-09-2016

Modelsim doesn't include PLL simulations. Just write a test bench that generates the clocks you need.

A PLL is a hybrid analog/digital circuit and Modelsim supports only digital so it wouldn't be able to do an accurate PLL simulation.

Altera_Forum · ‎08-10-2016

Thank you for answer, Galfonz!

Yes, I know - PLL is mixed part. But Altera has example - this one (https://www.altera.com/support/support-resources/design-examples/design-software/simulation/modelsim/exm-pll-simulation.html). Important - step of simulation should be 1 ps! And I have done it (did do? I'm not sure) successful for VHDL, not schematic (see details in first post). than i forgot it , because it was about month ago and this month i needed take a pause. so, will try remember.

Any idea?

Altera_Forum · ‎08-10-2016

Sorry, I've not looked into it beyond using a test bench or wave entries.

Altera_Forum · ‎08-10-2016

Gate level mode uses the netlist - which would include the pll in compiled form and not simulatable. The VHDL code will include a PLL model

WHy do you need to simulation the PLL? the model runs very slow and if all you need is a clock then you can just generate it yourself ina testbench.

Altera_Forum · ‎08-10-2016

how did I do it in VHDL? Possible, it will useful some people.

1) Generate new project where assignment-settings-simulation format for output netlist set to VHDL

2) Create top-level file (see main below)

3) tools-megawizard plugin, generate our PLL, for example: in 25MHz, out - 100MHz

4) Compile, processing-start-start analysis and elaboration, next tools-run eda simulation - gate level

5) In Modelsim expand "work", select our module (x_pll), create dummy wave and delete all output signals.

6) right click on module, select 'Simulate' and now draw real waves. If try do it on previous step, MS mixed ns and ps.

7) drag-n-drop output signals to wave window. Correct run lenght 100 ps to 1 ps - this one I'm not sure.

8) menu simulate-run-run -all

It is done!

If somebody can give me advise how to optimize it - I will glade.

If I choose system verilog and 1 ps on step# 1 - ModelSim lost libraries!

2 tricky:

You are right - I need clock. how correct do it? And - I have done it for VHDL but how to do the same for schematic I don't know still.

-- Try to simulate PLL 
-- t.oleg(a)ymail.com
library ieee;
use ieee.std_logic_1164.all;
entity x_pll is 
 PORT( 
 x_clk: in std_logic;
 x_rst: in std_logic;
 x_c0: out std_logic;
 x_lock: out std_logic );
end entity;
architecture RTL of x_pll is
 component amf_pll
  PORT(
  areset: in std_logic;
  inclk0: in std_logic;
  c0: out std_logic;
  locked: out std_logic );
 end component;
 signal c0_sig, i_locked: std_logic;
begin
pll_mf: amf_pll PORT MAP (
        areset     => x_rst,
        inclk0     => x_clk,
        c0     => c0_sig,
        locked     => i_locked
    );
 x_lock <= i_locked;
 x_c0 <= c0_sig when (i_locked='1') else '0';    
end RTL;

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