How to solve error "174077:on chip termination control block is associated with conflicting I/OS"?

[SPraj4]

I am trying to design ddr3 interface using Qsys in Quartus Prime Lite Edition for cyclone V GT (5CGTFD9E5F35C7) Development board. While running I/O assignment analysis, I am facing this error. I am not able to understand what causing this error and what should be done in order to solve it .

[sstrell]

Did you run the pin_assignments.tcl script generated by the memory IP? This creates the correct I/O assignments for the interface.

#iwork4intel

[Kenny_Tan]

Which is correct, you need to run the tcl scripts. Only arria 10 and S10 you do not need to run the tcl scripts.

[SPraj4]

Yes I did run it.

[Kenny_Tan]

Can you attached your design.qar for us to look into it?

[Kenny_Tan]

Any update?

[SPraj4]

yes I am able to compile it now with 0 errors and some warnings. and working on next step -timing analysis ...but it taking so much time, I facing few setup violations etc.

[Kenny_Tan]

Great to hear that.