Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to solve error "174077:on chip termination control block is associated with conflicting I/OS"?

SPraj4
Beginner
1,659 Views

I am trying to design ddr3 interface using Qsys in Quartus Prime Lite Edition for cyclone V GT (5CGTFD9E5F35C7) Development board. While running I/O assignment analysis, I am facing this error. I am not able to understand what causing this error and what should be done in order to solve it .

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sstrell
Honored Contributor III
1,338 Views

Did you run the pin_assignments.tcl script generated by the memory IP? This creates the correct I/O assignments for the interface.

 

#iwork4intel

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Kenny_Tan
Moderator
1,338 Views

Which is correct, you need to run the tcl scripts. Only arria 10 and S10 you do not need to run the tcl scripts.

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SPraj4
Beginner
1,338 Views

Yes I did run it.

 

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Kenny_Tan
Moderator
1,338 Views

Can you attached your design.qar for us to look into it?

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Kenny_Tan
Moderator
1,338 Views

Any update?

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SPraj4
Beginner
1,338 Views

yes I am able to compile it now with 0 errors and some warnings. and working on next step -timing analysis ...but it taking so much time, I facing few setup violations etc.

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Kenny_Tan
Moderator
1,338 Views

Great to hear that.

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