I am trying to design ddr3 interface using Qsys in Quartus Prime Lite Edition for cyclone V GT (5CGTFD9E5F35C7) Development board. While running I/O assignment analysis, I am facing this error. I am not able to understand what causing this error and what should be done in order to solve it .
yes I am able to compile it now with 0 errors and some warnings. and working on next step -timing analysis ...but it taking so much time, I facing few setup violations etc.