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Altera_Forum
Honored Contributor I
2,157 Views

How to use Shared Variable

Tell how you use Shared Variable 

 

 

What you think about Shared Variable 

 

 

What they for
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21 Replies
Altera_Forum
Honored Contributor I
324 Views

The main use for shared variables is in test benches 

 

have a look at OSVVM. ORG 

 

the free packages there make extensive use of SHARED VARIABLES 

 

 

They are also very useful verification packages. 

 

creating good stimulus is often a lot of work & is boring. 

 

SAVE YOURSELF A LOT OF WORK 

 

have a look at intelligent coverage at OSVVM. ORG 

 

Those packages can create intelligent random functional coverage stimulus for you. 

 

With very little effort from you they can create stimulus for all the functions you ask them to cover in your testbench. 

 

The OSVVM packages are written by Jim Lewis & he leads the IEEE VHDL standard group who are working on the next version of VHDL after VHDL2008.
Altera_Forum
Honored Contributor I
324 Views

Thank 

 

Is any other person have OSVVM opinion
Altera_Forum
Honored Contributor I
324 Views

A shared variable is just a variable that can be used in several processes, similar to a signal, but it will update immediately. 

In VHDL 93, they could be declared for any type, but in 2002 onwards shared variables must be a protected type. (this rule is ignored by default in modelsim/quartus to maintain backwards compatability).  

Shared variables can be used to infer write-before read behaviour in infered rams rather than using a signal. 

 

On the testbenching side - they can be used with protected types (like OSVVM) so that you have variables with some behaviour simular to OO programming, although there are many restrictions. 

 

What are you goals, as this is a very open question. In FPGAs, they are most often used for ram behaviour inference, as I specified above. 

 

Be warned though, if used incorrectly, they can become prone to compile order dependency. Consisder the following: 

 

shared variable a : std_logic; process(clk) begin if rising_edge(clk) then a := '1'; end if; end process; process(clk) begin if rising_edge(clk) then a := '0'; end if; end process;  

 

here, you have no idea if "a" will end up as '1' or '0', as you do not know which process will act on the variable last. There are no 'X' values to denote unknown in simulation as its down to the compiler which process "wins". (quartus will throw multiple driver error though)
Altera_Forum
Honored Contributor I
324 Views

Thank tricky good info 

 

Is any other person have opinion
Altera_Forum
Honored Contributor I
324 Views

 

--- Quote Start ---  

Thank tricky good info 

 

Is any other person have opinion 

--- Quote End ---  

 

 

As for an opinion - just dont use them in synthesisable code. Stick to signals like everyone else.
Altera_Forum
Honored Contributor I
324 Views

As I said above 

The main use for shared variables is in test benches 

 

the free OSVVM packages make extensive use of SHARED VARIABLES 

 

You will find this webinar very useful 

 

https://www.doulos.com/content/events/adv_vhdl_verification.php
Altera_Forum
Honored Contributor I
324 Views

Here is another OSVVM Shared Variable Webinar Link for You 

 

I was going to post it last week but I couldn't find it. 

 

This shows how VERY useful Shared Variables can be in testbenches. 

 

www.aldec.com/en/support/resources/multimedia/webinars/1719
Altera_Forum
Honored Contributor I
324 Views

Thank Tricky 

 

thank DoItRight 

2 webinar you link GOOD GOOD GOOD 

 

see good info in 2 webinar
Altera_Forum
Honored Contributor I
324 Views

Is any other person have opinion

Altera_Forum
Honored Contributor I
324 Views

In what context are you looking at? 

There is NO REASON to use a shared variable in synthesis code - other than for a write-before read ram inference 

There are loads of reasons to use them in testbenches. 

 

What are you trying to do?
Altera_Forum
Honored Contributor I
324 Views

SHARED VARIABLES can help you to solve really difficult PSL Assertion problems. 

 

 

Say you need a Signal or a Sequence Seq1 to Occur Twice in an antecedent & the SECOND Occurrence MUST then be followed by another Sequence Seq2. 

THEN 

You DO NOT WANT Another thread to start <<<<<<<<<<< 

UNTIL 

After the SECOND Occurrence of Seq1 & then the Occurrence of Seq2. 

 

 

 

 

System Verilog's First Match 

OR 

PSL's goto repetition ie. [->] 

Will NOT STOP the UNWANTED thread starting on the SECOND Concurrence of Seq1. 

 

 

Unwanted threads can be avoided. 

HOW? 

 

 

Create a shared variable that has the following functions (methods). 

 

 

type PSL_BOOL_PType is PROTECTED 

impure function get( Get_Enable : BOOLEAN ) return BOOLEAN; 

impure function clr( Clr_Enable : BOOLEAN ) return BOOLEAN; 

impure function set( Set_Enable : BOOLEAN ) return BOOLEAN; 

end PROTECTED PSL_BOOL_PType; 

 

 

These all Return the State of the BOOLEAN variable inside the PROTECTED BODY 

BEFORE 

the function was called. 

 

 

I'll leave you to write the PROTECTED BODY. 

 

 

Declare Your_Shar_Var 

shared variable Your_Shar_Var : PSL_BOOL_PType; 

 

 

You can then use Your_Shar_Var to DISABLE the triggering of new threads for your assertion by using  

Your_Shar_Var.clr(rose(Last))  

in the antecedent 

Where 

Last is the Last signal to rise in Seq1. 

 

 

You then need another property that includes:- 

 

 

{rose(Last):ended(Seq1)} |->  

Seq2 : (Your_Shar_Var.set(TRUE) or TRUE) -- ORDER of eval Means Your_Shar_Var.set MUST Come 1st 

}  

 

 

This not only checks for Seq2 

but ALSO 

Re-enables the triggering of new threads. 

 

 

************ 

* IMPORTANT 

************ 

PSL has LEFT to Right ORDER of evaluation 

SO 

This Means these Functions (Methods) MUST 

Sometimes Come FIRST ie. on the LEFT of an EXPRESSION 

OTHERWISE, they May NOT GET CALLED. 

 

 

There is a neater way of  

doing 

Seq2 : (Your_Shar_Var.set(TRUE) or TRUE) 

but 

it it requires another function. 

 

 

There really should have been a simple built in way of doing this in PSL & SVA 

BUT 

As I said above 

First Match OR goto repetition [->] WILL NOT DO IT. 

 

 

.............................................................. 

 

 

PSL was developed from IBM Sugar 

SVA syntax is almost the same as PSL 

BUT 

JUST TO BE DIFFERENT & INCOMPATIBLE 

They changed a few things like putting the Clock at the beginning of a property & stuff like# #1 

THERE WAS NO EXCUSE FOR THIS. 

 

 

UNFORTUNATELY 

All 3 Languages use the most APPALLINGLY BAD CRYPTIC SYNTAX 

BUT 

We are stuck with it.
Altera_Forum
Honored Contributor I
324 Views

Have you tried this type of Assertion aux code with a formal analysis tool? Does it work? 

I have used JasperGold breifly and the general consesus was to simplify assertertions as much as possible, and remove all aux code out of the assertions. The simpler the assertion (ie. no functions etc) the faster it will complete.  

 

Ideally you want  

a -> b
Altera_Forum
Honored Contributor I
324 Views

Tricky, 

 

I have not had the Luxury of trying it on a Formal Verification Tool. 

 

It simulates just fine. 

 

In other cases, this kind of technique certainly SPEEDS UP simulation by avoiding REDUNDANT THREADS in badly written very INEFFICIENT PROPERTIES when someone has dumped them on me & I don't have time to fix them. 

BUT 

in those cases I don't leave the aux code in the files, I just use it to investigate the problems. 

 

People who write INEFFICIENT PROPERTIES just don't care about how long we have to wait. Their attitude is that their properties do check & it is someone else's problem if the project is delayed.  

 

 

I would be very interested to know if JasperGold or VC Formal etc. can handle PSL_BOOL_PType properly. 

 

If there is anyone out there reading this & with access to Formal Verification Tools then please TRY IT OUT & let us all know. 

 

In THEORY, if those tools implement VHDL2008 PROPERLY then all should be well. 

 

Tricky, maybe you could try it with JasperGold. 

 

 

PSL_BOOL_PType is a very simple Protected Type & once created it can be used over & over again without much effort. 

 

Using aux code feels like a bit of a Kludge but we have to live in the real world. 

I could say the same thing about PSL & SVA. (Double Kludge) 

 

ANYWAY 

For the situation described in my previous post we really SHOULD NOT have to do this. 

 

There SHOULD have been a simple BUILT IN way of doing this in PSL & SVA 

BECAUSE 

As I said before 

First Match OR goto repetition [->] WILL NOT DO IT.
Altera_Forum
Honored Contributor I
324 Views

I no longer have access to JG - it was temporary. 

Protected types are VHDL 2002, not 2008. So should work with JG. 

 

From my JG training - AUX code is a necessity. But anything that prevents separate threads being needed is what you have to do for formal. JG doesnt really support anything clever in asserts - otherwise the prove time just explodes. Aux code also increases the State space, so making it non-synthesisable probably wont really work with JG. All AUX code I have seen for JG was basically synthesisable verilog (Ive only worked with SVA).
Altera_Forum
Honored Contributor I
324 Views

I said VHDL2008 because of the PSL 

 

I doubt that old tools that had to have PSL in comments would work.
Altera_Forum
Honored Contributor I
324 Views

Tricky ask what I try to do? 

 

I learn
Altera_Forum
Honored Contributor I
324 Views

Thank Designer123 

 

Good info 

 

I try it and it work
Altera_Forum
Honored Contributor I
324 Views

 

--- Quote Start ---  

Tricky ask what I try to do? 

 

I learn 

--- Quote End ---  

 

 

Like I said in post. 

For synthesis, they're pretty useless. 

So unless you explain why you want one, it's difficult to help..
Altera_Forum
Honored Contributor I
324 Views

Tricky 

I not want one 

 

I learn all part of VHDL 

I want job in new team
Altera_Forum
Honored Contributor I
93 Views

There are plenty of tutorials out there. There are a lot of things you can do with a Shared variable, so without specific questions or problems it is too big a topic to answer.

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