Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to workaround the ERROR ID:18694

LChen23
Beginner
1,580 Views

Hi,

When I switch Quartus from 18.1std to 19.4 Pro,Quartus report an error, The ID is ID:18694

ID:18694 The reference clock on PLL "<name>", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

 

because of the no clk from Dedicated reference clock , I use Pll cascade.

 

My quest is how to work around it ? I hope to use Quartus Pro .

Thanks.

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Rahul_S_Intel1
Employee
1,463 Views

Hi ,

Kindly fine the inline reply

CAUSE: PLLs driving LVDS SERDES interfaces should use dedicated reference clock pins from the same bank. Using a different source such as a global clock or PLL cascading can add extra jitter and has not been fully verified and characterized by Intel. It is therefore not guaranteed to meet its max data rate specification.

ACTION: Use a dedicated reference clock pin per PLL that drives an Altera LVDS SERDES IP instance.

 

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Rahul_S_Intel1
Employee
1,463 Views

Hi ,

Kindly let me know, if you need further assistance.

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FvM
Valued Contributor III
1,050 Views
Hello,
quoted error message states the requirement of using a reference clock input from the same IO bank. The statement seems to contradict Cyclone 10 GX manual that optionally allows a reference clock of a different bank. No doubt that clock routing involves additional jitter, but we are not neccessarily talking about maximal data rate. Just to reenable functionality specified in user manual and remove an obviously erroneous error message that hasn't been there in previous Quartus versions. Unfortunately it's still present in QPP 22.4.
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