Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

I/O Register Packing

TuckerZ
New Contributor I
877 Views

Hello, 

 

I wanted to get a conceptual understanding of how I/O Register Packing works. I was reading the Intel® Quartus® Prime Standard Edition User Guide: Design Compilation version 2018.09.24 and section 1.10.13 talks about I/O Register Packing when it comes to cross-partition register packing of I/O registers. 

 

 I have found the definition for register packing. I understand I/O Register Packing to work by taking the register that is connected to an input or output of a pin of the device and moving it to be contained in the I/O Cell (I/O Element) near the periphery of the device instead of a Logic Element (LE). 

 

Is that a correct assessment? 

 

When it comes to cross-partition register packing, does that mean that Quartus will break the partition boundaries to attempt to do what I described above? 

 

Thank you ahead of time for any clarification!

THZ



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sstrell
Honored Contributor III
864 Views

Your assessment is correct.

When you are talking about "cross-partition register packing", I assume you are talking about design partitioning.  This part of the user guide explains it: https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/i-o-register-packing.html

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sstrell
Honored Contributor III
865 Views

Your assessment is correct.

When you are talking about "cross-partition register packing", I assume you are talking about design partitioning.  This part of the user guide explains it: https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/i-o-register-packing.html

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TuckerZ
New Contributor I
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@sstrell @ShengN_Intel  

 

Thank you for the information. 

 

Does the Design Floorplan and LogicLock affect Quartus' ability to perform cross-partition register packing? If so, how? 

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ShengN_Intel
Employee
856 Views

Hi THZ,


Let me know if you have any further concern or consideration on this thread.


Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.


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ShengN_Intel
Employee
768 Views

Hi,


The Cross-Boundary Optimization is applicable to Logic Lock region. Therefore LogicLock does not affect Quartus' ability to perform cross-partition register packing. The difference between design partition and logic lock is just logic lock can assign the logical design partition to a particular physical region in the device floorplan check this link https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/the-difference-between-logical-partitions.html


Thanks,

Best Regards,

Sheng


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