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ZC0001
Beginner
419 Views

I am confused about the Equation 5 in the AN433

Hi,all.

I am currently learning about FPGA interface constraints. 

Now I am confused about the Equation 5 in the AN 433: Constraining and Analyzing Source-Synchronous Interfaces.I don't know how to understand this equation.

looking forward your help.

Best Regards.

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6 Replies
IDeyn
New Contributor III
124 Views

Hi ZC0001!

 

First of all, I want to say that in my opinion Source Synchronous Interfaces better to understand using Intel FPGA free training video - Constraining Source Synchronous Interfaces (OCSS1000)

https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html

 

As about your particular question, It should be understand, for example, like that.

 

 

Your case is FPGA-Centric Output Delay Constraints. In case of Edge-aligned transfer, the difference between latch and launch edge is zero,

so you only need to put into account clock arrival time - maximum delay of data, which is essentially the difference in delays from FPGA clock and data paths to external device.

 

Hope it helps.

 

You can ask for more detail if my explanation is not useful.

 

--

 

Best regards, 

 

Ivan

ZC0001
Beginner
124 Views

Hi, IDeyn

 

Thanks for your reply.

 

I think i already understand why in the equation subtracting 'maximum delay of data' instead of tSU. Because the required time refers to the time when the data arrival at the FPGA output pin , not the time when the data reaches the external chip pin.

 

I don't know if I understand it correctly.

 

Best regards.

 

​ZC

IDeyn
New Contributor III
124 Views

Hi ZC0001!

 

Hmmm, I also don't know if you understand correctly)

 

The main thing is that when you will write set_output_delay constraint, you will also take into account the path to the external chip.

So the idea is to constraint maximum skew between clock and data form the FPGA to external chip.

 

--

 

Best regards, 

 

Ivan

 

AnandRaj_S_Intel
Employee
124 Views

Hi,

 

Before understanding equation 5. Try to understand the setup, hold & slack time and how to achieve it.

Aslo refer

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

 

Regards

Anand

ZC0001
Beginner
124 Views

Hi, Anand

Thanks for your reply.

I think i can understand the setup,hold and slack time correcctly. I am comfused about the equation 5 or the skew method because i don't konw why using 'maximum/minimum delay of data to calculate the required time of data . Now I think this is because the required time is the time when the data arrival at the FPGA output pin , not the time when the data reaches the external chip pin.

I don't know if I understand it correctly.

Thanks again.

​ZC

AnandRaj_S_Intel
Employee
124 Views

Hi ZC,

 

it is till data reaches the external chip pin.

Refer page 46.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf

 

Regards

Anand

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