It seems that the UFM does not allow me to initialize it to a .dat file for simulation using Modelsim. In fact it appears that it does not even accept my .dat file or even the defaullt ufm_onchip_flash_0.dat file as mentioned in the IP Editor for the UFM that I cannot locate in any files. I cannot find the UFM hw.tcl that I expected to see anywhere. Also, in the altera_onchip_flash.v file while the parameter INIT_FILENAME_SIM can be set to my .dat file which I have done, after compilation it reverts back to "".
For initializing UFM refer the below link,
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
(This message was posted on behalf of Intel Corporation)
I hve in fact used the On-Chip Flash Intel FPGA IP Core (thru Platform Designer) to initialize the UFM with a .mif file and a .dat file for simulation.
- For Initialize flash content selected without my custom init files it says as follows. "The on-chip flash will be initialized from the ufm_onchip_flash_0.hex
ufm_onchip_flash_0.dat for simulation "
However I cannot find these files anywhere . If I could at least locate
these files I could compare the .hex to the .dat files to each other which I
could then use as an example to create my own .dat file. Why are they
not present? Right now I have my own custom .mif and .hex file but no
.dat file. Can you advise me as to their path or otherwise just send
them both to me?
The Embedded Design Handbook and the Convert Programming Tool
refer to .sof and .pof and in regards to NIOS which I am not using in my
project. I just need simply to go from .hex to .dat. I have seen hex2bin
apps available but is a .dat format required for simulation equivalent to a
also, 2. There does exist an "INIT_FILENAME_SIM" field in the
altera_onchip_flash.v file that is initially set to "". It is supposed to be
automatically set to "MyFileName. dat" upon finishing with the
Platform Designer for the UFM but it remains at "" so it does not
seem to accept any file names for init sim that I entered into Platform
Designer so there could be an issue with the UFM IP Core Generator or
also, 3. I was advised to make changes to the Set_module_assignment
postgeneration.simulation.init paramater in the hw_tcl file. There is no
hw_tcl file present for the UFM. Hoever I can it one using Platform
but then the generated ufm_hw.tcl file does not contain the said
paramater so still I cannot affect it.
Thanks for responding. However I am not using Nios for this project nor am I doing reconfiguration as this video focuses on.
I am more concerned with the ability to simulate a project showing activity of the UFM signals especially its avmm_readdata output
as the address increments along with the proper control signals. Except for the avmm_readdata output always being shown as xFFFFFFFF
the other signals seem correct to me in ModelSim. I believe that the UFM using the Platform Designer (QSYS) was implemented correctly.
If there was an example for ModelSim simulation available for me to follow it would be helpful but I have not found any. I did find an project example
using the Signal Tap Analyzer with documented waveforms that should run on the MAX 10 FPGA Development kit. We just ordered this kit so I hope to soon excersize this example while learning the Signal Tap Analyzer.
It would have been so much easier to just simulate with ModelSim which I could immediately do since I am familiar with this tool.