Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15547 Discussions

I am using a Cyclone V GT and CVP on PCI Express. I have programmed the flash and uploaded the core.rbf. I am trying to use signal tap to look at signals in the core. Signal Tap application shows "invalid JTAG configuration". Suggestions?

jmelv
Novice
1,232 Views

 Is there a sample project showing the use of Signal Tap in the core uploadable partition?

0 Kudos
1 Solution
jmelv
Novice
202 Views

Hi Nooraini,

 

Thanks for the reply.  I finally found the answer, you can’t put a signal tap instance in the CVP core partition in a Cyclone V. It has to reside in the top partition so to tap nodes in the CVP core partition, signals have to be passed up to the Periphery (top) .

https://www.intel.com/content/www/us/en/programmable/quartushelp/14.1/mergedProjects/msgs/msgs/wsgn_...

 

A note added to the CVP documentation for Cyclone V about using SignalTap to look at core partition signals would be helpful for anyone trying this in the future.

 

View solution in original post

3 Replies
Nooraini_Y_Intel
Employee
202 Views

Hi Jmelv,

 

Have you try to test the SignalTap without using the CvP mode first? Test the full image configuration either from JTAG or AS/PS/FPP mode then test the SignalTap if it works or not. If the does not work with the same "invalid JTAG configuration", the potentially the db (database) could be corrupted. What do you mean "uploadable" partition?

 

Regards,

Nooraini

jmelv
Novice
203 Views

Hi Nooraini,

 

Thanks for the reply.  I finally found the answer, you can’t put a signal tap instance in the CVP core partition in a Cyclone V. It has to reside in the top partition so to tap nodes in the CVP core partition, signals have to be passed up to the Periphery (top) .

https://www.intel.com/content/www/us/en/programmable/quartushelp/14.1/mergedProjects/msgs/msgs/wsgn_...

 

A note added to the CVP documentation for Cyclone V about using SignalTap to look at core partition signals would be helpful for anyone trying this in the future.

 

Nooraini_Y_Intel
Employee
202 Views

Hi Jmelv,

 

Yes you are correct on this. The SignalTap need to be place at the top partition part of the periphery.

 

Regards,

Nooraini

Reply