I am using quartus pro 18.1 I get a error unconstrained ports can only be associated in whole if I cast a unconstrained std_logic_vector to an unsigned for my generic memory

[bswag]

I have memory block

I have memory as follows:

entity memory is

port

(

clk : in std_logic;

din : std_logic_vector;

wr : in std_logic;

dout: std_logic_vector

);

When I instantiate for example

.

.

din_unsigned : unsigned(7 downto 0)

dout_unsigned : unsigned(7 downto 0);

.

.

begin

my_memory : entity work.memory is

  port map

(

clk => clk,

din => std_logic_vector(din_unsigned),

wr => wr,

unsigned(dout) => dout_unsigned

);

I don't think this is ambiguous, however the casting of the unstrained output causes an error 13726 unconstrained ports can only be associated in whole.

The workaround is using a dummy std_logic_ vector signal and a subsequent casting to unsigned.

Please fix this or enlighten me to the rationale for this rule.

[IDeyn]

Hi bswag.

There is a perfect reference about VHDL type casting - http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Hope it helps.

Best regards,

Ivan

[GuaBin_N_Intel]

Try to build similar coding and able to compile successfully in Pro 18.1. Did not have the error message.

************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cast_test is

  port

  (

clk,wren : in std_logic;

address : in std_logic_vector (7 downto 0);

    input : in unsigned(7 downto 0);

    output,q_out : out unsigned(7 downto 0)

  );

end entity cast_test;

architecture rtl of cast_test is

component RAM1P_w8 

port (

data  : in std_logic_vector(7 downto 0) := (others => '0'); -- ram_input.datain

address : in std_logic_vector(7 downto 0) := (others => '0'); --      .address

wren  : in std_logic          := '0';       --      .wren

clock  : in std_logic          := '0';       --      .clk

q    : out std_logic_vector(7 downto 0)           -- ram_output.dataout

);

end component;

component test 

  port

  (

    input : in std_logic_vector(7 downto 0);

    output : out std_logic_vector(7 downto 0)

  );

end component;

signal w_input : unsigned (7 downto 0);

begin

w_input <= input;

 test_inst : test

  port map (

   input => std_logic_vector(w_input),

   unsigned(output) => output

  );

RAM1P_w8_inst : RAM1P_w8 

port map(

data  => std_logic_vector(w_input),

address => address,

wren  => wren,

clock => clk,

unsigned(q)  => q_out

);   

end architecture rtl;

********************* Sub module ***************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity test is

  port

  (

    input : in std_logic_vector(7 downto 0);

    output : out std_logic_vector(7 downto 0)

  );

end entity test;

architecture rtl of test is

begin

 output <= not input;

end architecture rtl;

*****************************

[bswag]

Not quite similar my memory is unconstrained yours is constrained to length 8.

[GuaBin_N_Intel]

It is not allowed to constrain it with different bit width and have to include the port as a whole from what I understand https://www.intel.com/content/www/us/en/programmable/quartushelp/18.0/index.htm#msgs/msgs/evrfx2_vhdl_unconstraint_formal_partial_assignment.htm