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I am working with cyclone v fpga(5CEBA2F23C8) .While running it i got the below problems.

JGeor12
Beginner
333 Views

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PLL LVDS output(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (175001): The Fitter cannot place 1 PLL LVDS output.

Info (14596): Information about the failing component(s):

Info (175028): The PLL LVDS output name(s): lvdse:lvdse_inst|altlvds_rx:ALTLVDS_RX_component|lvdse_lvds_rx:auto_generated|pll_ena~PLL_LVDS_OUTPUT

Error (16234): No legal location could be found out of 8 considered location(s). Reasons why each location could not be used are summarized below:

Error (175006): Could not find path between source fractional PLL and the PLL LVDS output

Info (175026): Source: fractional PLL lvdse:lvdse_inst|altlvds_rx:ALTLVDS_RX_component|lvdse_lvds_rx:auto_generated|pll_sclk~FRACTIONAL_PLL

Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X0_Y1_N0

Error (175022): The PLL LVDS output could not be placed in any location to satisfy its connectivity requirements

Info (175029): 4 locations affected

Info (175029): PLLLVDSOUTPUT_X0_Y38_N2

Info (175029): PLLLVDSOUTPUT_X0_Y39_N2

Info (175029): PLLLVDSOUTPUT_X54_Y38_N2

Info (175029): PLLLVDSOUTPUT_X54_Y39_N2

Error (175006): Could not find path between the PLL LVDS output and destination pin

Info (175027): Destination: pin lvdse_in[0]

Info (175015): The I/O pad lvdse_in[0] is constrained to the location PIN_G6 due to: User Location Constraints (PIN_G6)

Info (14709): The constrained I/O pad is contained within this pin

Error (175022): The PLL LVDS output could not be placed in any location to satisfy its connectivity requirements

Info (175021): The pin was placed in location pin containing PIN_G6

Info (175029): 4 locations affected

Info (175029): PLLLVDSOUTPUT_X0_Y1_N2

Info (175029): PLLLVDSOUTPUT_X0_Y2_N2

Info (175029): PLLLVDSOUTPUT_X54_Y1_N2

Info (175029): PLLLVDSOUTPUT_X54_Y2_N2

Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

 

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1 Reply
RichardTanSY_Intel
136 Views

Hi, you can refer to the below forum case for the solution.

Let me know if it helps.

 

https://forums.intel.com/s/question/0D50P00003yyJiESAU/pin-placement-with-altera-lvds-core?language=...

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