I got the following warning 10240 inferred latch on a variable. Is this a problem? if so how do I fix it.

[JBurt2]

module SPI_OUTPUTS(input ReSet,

  input SPI_CLK,SPI_CS,SPI_DIN,output SPI_DOUT,output reg [24:1] Outputs = 0);

reg [23:0] SPI_shift = 0; //SPI Shift Reg

reg Start = 0;

assign SPI_DOUT = (Start == 0) ? Outputs[24] : SPI_shift[23];

always @(posedge SPI_CLK or posedge SPI_CS or negedge ReSet) begin

 if (ReSet == 0) begin

  Outputs[24:1]  <= 0;

  SPI_shift[23:0] <= 0;

   Start       <= 0;

 end else begin

  if (SPI_CS == 1) begin //On Pos Edge of CS save spi_shift reg

   if (Start)

    Outputs[24:1]  <= SPI_shift[23:0];

   SPI_shift[23:0] <= 0;

   Start <= 0; 

  end else begin

   if (!Start)

    SPI_shift[23:1] <= Outputs[23:1];

   else

    SPI_shift[23:1] <= SPI_shift[22:0];

   SPI_shift[0] <= SPI_DIN;

   Start      <= 1;

  end

 end

end

endmodule

[AndyN]

I would say the source of your problem is using SPI_CS in the sensitivity list. Are you really meaning to do that or can you sample it synchronously with the posedge of the clock?

[a_x_h_75]

Whether it's a 'problem' is for you to determine. Generally latches should be avoided because it's very tricky to determine if they will cause timing issues. Sometimes designs require latches. In these cases you need to be careful and ensure they work by design and not rely on timing paths.

In your case there is certainly no need for a latch. I agree with ANico1 - redesign the code having removed SPI_CS from your sensitivity list. You should then have a synchronous design - without latches.

Cheers,

Alex