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I have configured a GXB transceiver to be RX Simplex. I get the next error message in Quartus 18.1 Pro
Error(14566): The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 HSSI_DUPLEX_CHANNEL_CLUSTER(s)). Fix the errors described in the submessages, and then rerun the Fitter. Error(175020): The Fitter cannot place logic HSSI_DUPLEX_CHANNEL_CLUSTER that is part of Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP gxb_rtx_altera_xcvr_native_a10_181_lfm4w2i in region (224, 6) to (224, 23), to which it is constrained, because there are no valid locations in the region for logic of this type. Info(14596): Information about the failing component(s): Info(175028): The HSSI_DUPLEX_CHANNEL_CLUSTER name(s): gxb_rtx_i|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_buf.inst_twentynm_hssi_pma_rx_buf~HSSI_RX_CHANNEL_CLUSTER0~HSSI_DUPLEX_CHANNEL_CLUSTER0
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info(175015): The I/O pad FMC_RX_P[0] is constrained to the location PIN_AW7 due to: User Location Constraints (PIN_AW7)
Info(14709): The constrained I/O pad is contained within a pin, which is contained within a HSSI_RX_CHANNEL_CLUSTER, which is contained within this HSSI_DUPLEX_CHANNEL_CLUSTER
Error(18695): Could not find a legal chained placement. (1 location affected)
Info(175029): HSSI_DUPLEX_CHANNEL_CLUSTER containing PIN_BC7
What are the steps to take to solve this error or is this a tool bug?
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Hi,
As I understand it, you are observing some Fitter error in your design related to simple Native PHY RX. This seems to be related to the placement rules. To facilitate further debugging, would you mind to help sharing with me a simple test design with only the Native PHY instances which could replicate similar error. This would allow us to focus only on Native PHY and isolate out non-XCVR related logic or module.
It would be great also if you could share with me a high level XCVR placement that you are trying to implement ie where is the RX/TX/duplex XCVR placed in a XCVR bank together with the target data rate so that I could have a better understanding on your placement.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
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Hi Guido,
By the way, it seems like I am unable to locate your attachment of design. Would you mind to reattach? thank you very much.
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Hi Guido,
Sorry for the delay. I have been out for the past week. It seems like I am still unable to see the ZIP attached. However, as I understand it, Armin has also helped to file an IPS case on behalf of you on this and we have shared the resolution through the IPS case. To facilitate subsequent discussion and tracking purpose, it would be great that we use the IPS for further follow up.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
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Hi Guido,
Thanks lot. Please feel free to let me know if you have any issue in getting update. Thank you.

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