Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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I having problem with University Program VWF.

liyana
Beginner
894 Views

I can run the functional simulation waveform but the output is always 0000. How can I fix that? I use Quartus II 18.1 version. 

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4 Replies
SyafieqS
Moderator
845 Views

Do you mind to post some snippet and of the code and tb?


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liyana
Beginner
830 Views

This is the code that I use:

 

module register (clock , r_enable , w_enable, data_in, data_out);
input clock;
input r_enable;
input w_enable;
input [3:0] data_in;
reg [3:0] registerIS;
output reg [3:0] data_out;
always @(posedge clock)
begin
if (w_enable)
registerIS <= data_in;
else if(r_enable)
data_out <= registerIS;
end
endmodule

quartus1.jpg

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SyafieqS
Moderator
782 Views

Hello,


The problem with your code appears to be that you are not setting the output data_out otherwise; instead, you are only assigning a value to it when the r_enable input is high. The output data_out will thus keep its prior value, which in this case is uninitialized, resulting in 0000 output when the r_enable input is low.


The current value of registerIS can be assigned to data_out when r_enable is low by adding an else statement to your always block to address this problem. This will guarantee that, even when r_enable is low, data_out always represents the current value of registerIS.


Changes:


module register (clock, r_enable, w_enable, data_in, data_out);

 input clock;

 input r_enable;

 input w_enable;

 input [3:0] data_in;

 reg [3:0] registerIS;

 output reg [3:0] data_out;


 always @(posedge clock) begin

  if (w_enable) begin

   registerIS <= data_in;

  end

  else if (r_enable) begin

   data_out <= registerIS;

  end

  else begin

   data_out <= data_out;

  end

 end

endmodule



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SyafieqS
Moderator
715 Views

Let me know if there is any update or concern at your end.




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