What started as a design workaround when I found that ALTPLL in Verilog was broken is also useful in simulation. I feed an external clock into the simulator and don't instantiate the PLL and it runs the simulation something like 10x faster.
The downside is that I have to remember which way the include file is set or I'll generate a jbc file that won't work in hardware. The design is in maintenance mode and sometimes I forget everything that has to be touched. If there is a way to selectively run the jbc process, that would be great - that way if I don't instantiate the PLL, I also don't generate the jbc file and I can't waste time building it into firmware only to have nothing happen. Followed by my best Homer Simpson imitation: "D'oh!"
Lite Edition Version 18.0.0 Build 614 04/24/2018
The easiest thing would be to not have the Assembler, which generates the file, run during a full compilation. In the Pro edition, you can click a checkbox in the Compilation Dashboard, but in the Lite edition, go to Project menu -> Settings -> Compilation Process Settings and turn off "Run Assembler during compilation."
When you do need to generate the file, just run the Assembler manually from Processing menu -> Start -> Start Assembler.