this is the error "Error (10481): VHDL Use Clause error at clk_wiz_0_tmp.vhd(72): design library "unisim" does not contain primary unit "vcomponents". Verify that the primary unit exists in the library and has been successfully compiled".
I use Quartus 18.1
In the VHDL Desgin Files (.vhd), clk_wlz_0_tmp.vhd, you tried to access the specified primary unit of the specified design library. However, the design library does not contain the primary unit, or the primary unit has not been successfully compiled.
For example, the Use Clause in the following code attempts to access the primary unit example, but the ieee design library does not contain the primary unit example:
You can also refer to the forum case below:
I am not familiar with unisim library but I found this forum case that could help with your inquiry? Please refer to the link below.
Have you solved this problem？ I meet the same question now ，and when I copy unisim vhdl library from vivado to quartus library， but more detail errors were reported and some previous errors.
Do you have some suggestions or solutions？
Thanks very much！