i am trying to implement i2c protocol using VHDL Language. In my Case Master is Arria V FPGA & Slave is ADV7182.
The issue what i am getting is Acknowledgement. I am getting not Acknowledgement.
Please let me know what is my mistake in my VHDL code. i am getting struct now.
I suggest not using SCL_CLK as a clock. It is very slow compared to the FPGA clock and wont be a very good clock. Use the FPGA clock for everything and use the SCL_CLK you generate as a clock enable for the I2C registers.
>> The issue what i am getting is Acknowledgement. I am getting not Acknowledgement.
How do you know that? Your code appears to be incomplete.
Check your state machine.
If you receive an acknowledge from the slave, it goes into state x"06" that takes you to the WHEN OTHERS case with your state machine getting stuck.
I checked on CRO data what i am writing was correct but in acknowlegement clock cycle SDA was high
it should be low in acknowledgement clock cycle.
Well once it get the acknowledgement it should go to state 6 but it was going to ideal state i.e. state 0
So No acknowlegment.
Tricky : well may be you are correct ,Actually i have one doubt whether implementation of SDA is correct or not
and how can we say SCL_CLK will be one of the issue. any suspect you have for this.