IP_Compiler for PCI Express - timing constraints

[Altera_Forum]

Hi folks, 

 I'd like to check with you if the warnings I get are normal and if I should do anything else.  In QSys, I use the IP_Compiler for PCI Express configured for a hard IP of a Cyclone IV GX. It generates a file called altera_pci_express.sdc, which is added to the Quartus project. Here is its content:   create_clock -period "100 MHz" -name {refclk_pci_express} {*refclk_export}# SERDES Digital Reset inputs are asynchronous set_false_path -to {*tx_digitalreset_reg0c} set_false_path -to {*rx_digitalreset_reg0c} set_clock_groups -exclusive -group -group set_multicycle_path -end -setup -from 2; set_multicycle_path -end -hold -from 1; set_multicycle_path -end -setup -from ] 3; set_multicycle_path -end -hold -from ] 2;   Now, when I read that sdc file, I get these warnings:   Ignored filter at altera_pci_express.sdc(14): *refclk_export could not be matched with a port or pin or register or keeper or net or combinational node or node Ignored create_clock at altera_pci_express.sdc(14): Argument <targets> is not an object ID Ignored filter at altera_pci_express.sdc(16): *tx_digitalreset_reg0c could not be matched with a clock or keeper or register or port or pin or cell or partition Ignored set_false_path at altera_pci_express.sdc(16): Argument <to> is not an object ID Ignored filter at altera_pci_express.sdc(17): *rx_digitalreset_reg0c could not be matched with a clock or keeper or register or port or pin or cell or partition Ignored set_false_path at altera_pci_express.sdc(17): Argument <to> is not an object ID Ignored filter at altera_pci_express.sdc(18): *central_clk_div0* could not be matched with a clock Ignored filter at altera_pci_express.sdc(18): *_hssi_pcie_hip* could not be matched with a clock Ignored set_clock_groups at altera_pci_express.sdc(18): Argument -group with value contains zero elements Ignored set_clock_groups at altera_pci_express.sdc(18): Argument -group with value contains zero elements   Are these normal? I am not sure of the workflow usually used with such an IP, should I modify that sdc file by hand after generation to fix these issues? I found this (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05072014_784.html) in the knowledge base which I guess means usually we don't change the file. I did change the PCI Express refclk name to match the one in my top design, but remains the other warnings which I am not sure what to do with.  Thanks for the help,  Smith