I am trying to migrate an existing design from Stratix5 to Cyclone10Gx device.
Initial design was in Quartus Prime Standard Edition, however, while opening the project file in Quartus Prime Pro edition 20.3 (required for Cyclone10GX), an Upgrade IP Component window is popping up for migration of existing IPs used (copy attached for reference).
It does not enables the Auto Upgrade button. Moreover, from the description, it mentions to parameterize a supported IP core from catalog.
Kindly guide me to find the suitable IP Cores for the DDIO_IN, DDIO_OUT, SYSCLKPLL IPs which is supported in Cyclone10GX and steps to parameterize the same.
The PLL is easy: as stated, you have to delete the PLL from your design and add in the new one. I believe it's named IOPLL Intel FPGA IP.
For the DDIO, a migration flow for exactly what you're doing is described here: