Implementing static RAMs on Quartus block schematics (targeting MAX10)

[Valerius]

Hi all,

this is my first post here, very happy and excited to be part of this community

I'm doing my first FPGA project with a MAX10M08SCE144C8G device, since I'm not (yet) familiar with HDL (Verilog or VHDL) I'm tranlsating my TTL schematics to Quartus Prime (ver 17) block schematics.My design has some static RAMs that I'm unable to properly implement.I tried the IP megafunction but the resulting symbol has separate DATA INPUT and OUTPUT bus (while the real RAM has a single tristate bus), when I try to compie I get some errors complaining about tristate buffer (FPGA cannot have them internally IIRC).I also tried some Verilog/VHD models with single DATA bus I found on the net but none works.

I attach the snippet of the TTL schematics with RAMs hoping someone will help me.Thanks in advance.

[FvM]

Hi,
main problem in emulating static RAM isn't the bidirectional data bus, it's the fact that FPGA block RAM is synchronous, it uses a clock, at least all inputs (address, data, WE) are registered. This allows faster operation than asynchronous RAM, but external logic will look different.
As you already mentioned, there's no bidirectional bus inside the FPGA, but it can be emulated if it serves a purpose. External I/O pins can of course implement bidirectional I/O with tri-state, similar to discussed RAM.

[sstrell]

As mentioned, there is no tristate logic internal to the FPGA fabric, so your design is going to have to change, either by replacing with synchronous RAM blocks, as mentioned, or just registers.

[RichardTanSY_Intel]

As mentioned, memory blocks in Intel FPGAs are synchronous. Additionally, you may check out this user guide, 'Design Recommendations,' to help you in your FPGA journey.

https://www.intel.com/content/www/us/en/docs/programmable/683082/24-3/use-synchronous-memory-blocks.html

Regards,

Richard Tan

[RichardTanSY_Intel]

May I know if you need any further assistance regarding this case?

Regards,

Richard Tan