Hi,I am trying to fit an exponentiation algorithm which processes data of widths 4K bits at a time on a cyclone 2 chip. The number of logic elements are currently within the device specifications..the logic elements for the code after the analysis and synthesis stage stands as 42K/50K[Combination functions - 42K/50K, Dedicated logic registers - 21K/50K]. I dont think the verilog code can be optimized any further[and the chip cannot be changed]. Currently the Quartus II tool fails to proceed beyond the Fitter Routing stage. Though, I am getting the message saying Fitter placement was successful, routing is taking a lot of time and I get the message saying Final fitting attempt was not successful/Cant fit design in device. I am not sure what way I need to proceed to tackle this issue. I have gone through the chip planner. But I am not able to understand which specific piece of the code are causing the problems. This is my first project on an FPGA. Any suggestions which would help me to get in the correct direction would be helpful. If more information is needed to bring in more clarity please shoot back.
Sounds like the routing is getting conjested - do you have a lot of combinatorial logic? If it wont even finish the fit, the thing I can really think of is trying to pipeline as much as you can. Then maybe as a deeper step, look at logic lock regions. Design space exploration might be an option, but if it wont fit on a single run, using multiple seeds is unlikely to help.
Yes. The system has a lot of combinatorial logic. I am not able to reduce them as of now. I am not familiar with pipelining in FPGA and logic lock regions but I will surely look at them. Thanks for your suggestions.
Hi...I did change some of the additions using carry ripple adders which I guess is a sort of pipelining. I guess fitting placement is succesful [where the average interconnect usage is 61% and peak interconnect usage is 90% when using placement effort multiplier = 3]. However, I am still getting this error "Info (188005): Design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. The Fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. For more information, refer to the "Estimated Delay Added for Hold Timing" section in the Fitter report.". I do not see any such section in the XXX.fit.rpt and I am not sure how to interpret the results to check if something specific can be done to improve hold time requirements..any ideas ?
You have done nothing for pipelining. That requires putting registers between logic - not ripple adders.The easiest fix is at the code level, not messing around with logic. Add more registers!!!