Incremental compilation for transceiver (HSSI) on Cyclone 10 and Arria 10

[VFlav]

On my project, I develop 4 High-Speed Serial Interface (HSSI) which are connected to a FPGA Cyclone 10.

These interfaces are correctly worked, and I want now to fix the implementation on chip to save these design and to reduce compilation time.

My problem is to create a Design Partition with these 4 interfaces. I have to include them into the root partition because I use HSSI transceivers, Intel IP and HSSI-IO. But it seems than root partition cannot be saved and reused in others project (which are use same Cyclone 10 component).

Can you tell me if it is possible and if so, can you explain or redirect me on correct tutorial.

Thanks

[Kenny_Tan]

May I know which version of Quartus you are using? Quartus Pro or Quartus Standard? As each of them have a different flow.

[VFlav]

I'm using a Quartus Prime Pro 19.1.0 because Quartus Standard doesn't support Arria 10 and Cyclone 10 devices.

[Kenny_Tan]

Can you upgrade your design to 19.3? We have new feature call Fast Preserve option https://www.intel.com/content/www/us/en/programmable/documentation/lyx1569936504360.html

[sstrell]

You can use the root partition block-based design reuse flow. It is documented here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-block-based-design.pdf

And you can find an online training of the flow here:

https://www.intel.com/content/www/us/en/programmable/support/training/course/obbdr100.html

You can use the Fast Preserve option mentioned along with the design reuse flow to speed compile times, but you would need to move to at least 19.3. 

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