Inferring ROM with unregistered output

[Altera_Forum]

I am trying to infer ROM using a registered address but with unregistered output. No luck so far, ROM is not inferred unless I register the output. There is no message providing why it is not inferred (as it happens when you try to infer async RAM). I am using a Verilog case statement to define the ROM. 

 Quartus handbook suggests that ROM can be inferred as long as either the address or the output is registered. However it doesn't provide any example with unregistered output.

[Altera_Forum]

Is there a Quartus template that you can use? I know there is a Verilog ROM template but cannot recall whether it has output registers or not. Hope it doesn't:)

[Altera_Forum]

If you define a ROM with unregistered address and registered output, you're effectively creating a registered address and unregistered output, as far as see. Any reason not to go this way?

[Altera_Forum]

ARCHITECTURE Behav OF rom1 IS 

 CONSTANT Content: ROM_Array :=data;  BEGIN   PROCESS(clk,Address) BEGIN  IF(clk'event AND clk='1') THEN   Data_out <= std_logic_vector( to_unsigned(Content(conv_integer(Address)),width_data));   END IF; END PROCESS;   END Behav;    Quartus II 7.2 Infers a ROM with unregistered outputs

[Altera_Forum]

--- Quote Start ---  If you define a ROM with unregistered address and registered output, you're effectively creating a registered address and unregistered output, as far as see. Any reason not to go this way?  --- Quote End ---    No real compelling reason.  The reason I tried to avoid this is because it is counterintuitive. The timing and pipeline of the design are heavily based on the registered address. Furthermore, the registered addresss is used for other purposes besides indexing the ROM, so again, it seems more natural to register the address. Of course that registering the output is equivalent. Just that in this case, it makes less intuitive to understand the code and the simulation.  Btw, at one point I thought the reason that the ROM was not inferred, was because the registered address was being used for other purposes. This can't really be done on the hardware, because I understand the core can't access the registered side of the RAM address. Quartus would need to duplicate the register. But removing this behavior doesn't help. Seems like the only way is to register the output.    --- Quote Start ---    IF(clk'event AND clk='1') THEN   Data_out <= std_logic_vector( to_unsigned(Content(conv_integer(Address)),width_data));   END IF; ... Quartus II 7.2 Infers a ROM with unregistered outputs  --- Quote End ---    I'm not expert on VHDL, but I understand the code is actually using registered outputs, isn't it? I know that Quartus would "translate" this to registered address with unregistered output, which is equivalent. But that's not what I wanted (for reasons explained above).

[Altera_Forum]

Yes, the code by parrado shows unregistered addresses and registered outputs. But as I already mentioned, this RTL is mapped by Quartus to registered addresses and unregistered outputs, as you requested. 

 The designs timing is obviously defined by the real physical structure, not by the RTL. However, your idea, that the registered address value should be used for other purposes in the design, can't work, cause the address register is located inside the RAM block and can't be read. Thus the register would be duplicated anyway.  You may want the RTL representing the physical mapping as far as possible. Actually, I don't know why Quartus can't infer a ROM defined with registered addresses and unregistered output as such, although it uses this structure physically. I also don't know, why it seems to be unable to infer a dual port ROM.

[Altera_Forum]

If you need get the same address that is entering to the ROM, i suggest you should include a segmentation register in the address port; in this case you will have a timing equivalent address in the reamaining system. 

 I have used this solution in order to "access" the hidden registered address port of the rom.