Info 276004 with ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON

[FHint]

Hello,

I am trying to instantiate two RAM with a size defined by a generic g_desc_size. For this I use following statements in my VHDL code:

  attribute ramstyle              : string;
  type t_word                     is array (0 to 3) of std_logic_vector(31 downto 0);
  type t_desc_ram                 is array (0 to g_desc_size-1) of t_word;
  signal desc_ram                 : t_desc_ram;
  attribute ramstyle of desc_ram  : signal is "M20K";
  subtype t_wradr                 is std_logic_vector(63 downto 0);
  type t_wradr_ram                is array (0 to g_desc_size-1) of t_wradr;
  signal wradr_ram                : t_wradr_ram;
  attribute ramstyle of wradr_ram : signal is "M20K";

The generic can be 2 to 256, so the desc_ram can have a maximum size of 256x128 and the wradr_ram 256x64.

At first, when the info text mentioned in the subject line came up, I activated the ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION option. But after activation the line still appears:

Info (276004): RAM logic "<hierarchy path>|wradr_ram" is uninferred due to inappropriate RAM size

This only happens for the wradr_ram - the desc_ram is converted to an altsyncram megafunction.

Is there anything more I can do to force Quartus to implement the signal as a RAM?

I am using an Arria 10 FPGA and Quartus 19.1 Standard.

Best Regards,
Florian

[RichardTanSY_Intel]

Could you help to share your .qar design files so I could help to check on this? 

[FHint]

Hi,

thank you for the quick answer!

Unfortunately I can not provide the whole project, but I added to the .qar all the files I think are necessary for the issue. (qsf, vhd, tcl, qsys)

Best Regards,
Florian

[RichardTanSY_Intel]

Could you help to confirm whether there is files missing in the qar? 

I can't run Analysis and Synthesis due to missing files. Not sure if I miss anything? 
Try to duplicate the issue with the qar that was provided to confirm that it is duplicable, before attaching a new one. 

Warning (12019): Can't analyze file -- file ../../core/ip/x_protocol/clhsPack.vhd is missing
Warning (12019): Can't analyze file -- file ../../core/fpga_top/sib_nmi_clhs_fpga_top.vhd is missing

[FHint · Accepted solution]

Sorry, I only included the files that have direct impact on the problem and didn't check, whether the project was able to be built this way. But I have found the problem: the ST channel input port, that is connected to the read address of the RAM signal, was not driven by the ST source. Now that I have added logic in the source component RAM is being instanced. I still wonder why this was the cause though, because both RAM's read addresses mentioned above are driven by this ST channel input. Maybe it is because the one that worked is an asymmetrical RAM and Quartus handles them differently. Either way, it now works for both of them. Best Regards, Florian

[RichardTanSY_Intel]

Great to hear that you are making progress!!! 

Since the issue has been addressed, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.