Input/Output constraints

[Altera_Forum]

I've inherited a design that has no input/output constraints. The Quartus compiler flags the inputs and outputs as not having constraints assigned. I was wondering: if no input or output constraints are assigned, does the compiler assume it has a full clock cycle to route the signal in the FPGA or does it use any criteria at all? Thanks, Grady

[Altera_Forum]

Quartus won't assume anything. It will simply ignore all those paths when optimizing the design, and when reporting timing at sign-off.

[Altera_Forum]

Ok, thanks. So there is a possiblility that an input signal could be routed deep into the part so that its propagation delay from input pin to first flip-flop input could exceed a clock cycle? In this case, would looking at the detailed timing report be the only way to know?

[Altera_Forum]

Yes, the router can in theory route the signal all over the chip (even if that does not happen in practice). 

 Your solution is to add I/O constraints. You must have some kind of spec that you should be able to extract board timing from. Even if not, you can come up with some basic spec, even if it means assuming a global Tsu/Th/Tco spec.