Input Signals in ModelSim

Altera_Forum · ‎10-29-2014

Hi, I've started yesterday with ModelSim. Since I'm learning it my own and don't know who to ask, I'm posting this probably stupid question to you (sorry).

I saw when I have input signals to my verilog module, in ModelSim I'll have to explicitely set them, even to 0, alternatively they stay undefined. I read that I always should set not just the clock, but also a reset signal happening after certain period of time in the beginning. Now, I need a "start" impulse happening, and I noticed simply setting "start" to high after a certain time, leaves it high forever. So, I'm currently setting it then later to low. I'm trying to model here a 50 MHz clock.

Currently I'm doing it e.g. like this in transcript:


force -deposit /reset 0 0, 1 50 ns, 0 100 ns
force -deposit clk 1 0, 0 {10 ns} -repeat 20 ns
force /start 0 0, 1 100 ns, 0 200 ns

The module declaration looks as follows..


module algo(
    input clk,
    input start,
    input reset,
    output reg  leds,
    input write,
    input  writedata,
    output reg  readdata,
    output done
);

Questions:

Am I doing this actually correctly?

In my Verilog design should I also try to set signals to low when they're handled, e.g. the "start"?

When giving e.g. the start impulse, for how long actually should I leave it high in ModelSim?

Altera_Forum · ‎10-29-2014

better use an HDL testbench to drive your inputs. That force statements, deposits is not that helpful and better be thrown in to the river.

e.g.

clk initialised to zero...

clk <= not clk after 5 ns;

rst <= '0', '1' after 1000 ns;

and so on...

Altera_Forum · ‎10-29-2014

--- Quote Start ---

better use an HDL testbench to drive your inputs. That force statements, deposits is not that helpful and better be thrown in to the river.

e.g.

clk initialised to zero...

clk <= not clk after 5 ns;

rst <= '0', '1' after 1000 ns;

and so on...

--- Quote End ---

Thank you for the hint!! Probably my next obvious question now is, if you could recommend me one? I'm so happy to have found at least some possibility with ModelSim. Though it seems, if not re-opening it after an entire compilation, it shows some issues (line numbering might get messed up), but such things seem to be part of it, when working with FPGA / quartus ;)

Which HDL test bench would you recommend me?

Altera_Forum · ‎10-29-2014

--- Quote Start ---

Which HDL test bench would you recommend me?

--- Quote End ---

The one I am familiar with.

I haven't done verilog for 10 years now.

You can focus on vhdl like me and apply testbench to your design (vhdl or verilog or schematic) by instantiating it as component with testbench using vhdl port map syntax. However some licences of modelsim will not accept mixed language.

Altera_Forum · ‎10-29-2014

SystemVerilog would be a better testbench choice if your design is already in Verilog. Note that your testbench is only used in simulation, it should not be feed into Quartus.

Altera_Forum · ‎10-29-2014

Hum, but does it really make such a difference? I mean, I'm still really bloody and not using any highend features. Well, from what I see in ModelSim, typing / navigating this way as can be seen above is not really comfortable, but I've set up a script for it and so far it's really better than nothing. For the time being I'll stay to verilog, I already tried VHDL and probably will need an understanding of both +/-

To my question, when modeling a signal in ModelSim, e.g. start, for how many ns I should set it to high? Anyone has experiences with that?

Altera_Forum · ‎10-29-2014

--- Quote Start ---

To my question, when modeling a signal in ModelSim, e.g. start, for how many ns I should set it to high? Anyone has experiences with that?

--- Quote End ---

start is your own signal and you have decided to use it as input determined from outside the module.

but at least one clock period or more or for ever but never less than one clock depending on its purpose.