Instantiation of the module in a toplevel module

[Sijith]

Hi,

I was trying to understand the file structure and code dependencies in my Quartus Prime pro project "fifo". I have created a design in Platform Designer System with just an Avalon FIFO IP and was trying to simulate the output. 

I have a couple of questions. My working directory FIFO_TEST.zip is attached with this message.

1. I assume the module fifo_qsys_fifo_0 thatinstantiated in the top-level module \FIFO_TEST\fifo_qsys\sim\fifo_qsys.v is from \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\sim\fifo_qsys_fifo_0.v, right? I would like to know how the \FIFO_TEST\fifo_qsys\sim\fifo_qsys.v scans through folders to find fifo_qsys_fifo_0.v . 

2. I was going through the code \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\altera_avalon_fifo_181\sim\fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq.v, which I assume have an instantiation in  the \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\sim\fifo_qsys_fifo_0.v .  I saw a module fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq_single_clock_fifo, which has an instance of a module "scfifo" with a name  "single_clock_fifo". Basically I did not find any code in my working directory carrying a module "scfifo". May I know where this module is called from?

3. In my project, I selected the avalon streaming input to avalon mm read output port configuration.  I am bit confused with the assignments  in the fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq_map_avalonst_to_avalonmm module of  \FIFO_TEST\ip\fifo_qsys\fifo_qsys_fifo_0\altera_avalon_fifo_181\sim\fifo_qsys_fifo_0_altera_avalon_fifo_181_7tg32fq.v .

"assign avalonmm_data[7 : 0] = avalonst_data[31 : 24];
assign avalonmm_data[15 : 8] = avalonst_data[23 : 16];
assign avalonmm_data[23 : 16] = avalonst_data[15 : 8];
assign avalonmm_data[31 : 24] = avalonst_data[7 : 0];"

Is there any specific reason why the bits [31 : 24] in the Avalon streaming input data is assigned to the [7 : 0] bits of Avalon memory map output?.

4. I also would like to know what is the significance of the input parameter "fifo_0_out_address" in the avalon mm data transfer (please see \FIFO_TEST\fifo_qsys\sim\fifo_qsys.v). I am bit confused that since its a slave read port, and why we needed an address as input to FIFO?

I am curious that it has the name "address", but its just one bit wide. I would like to know how its value (setting 0 or 1) in testbench can affect the output data flow?

Thank you.

[sstrell]

Since you're talking about simulation, this is all about your simulation tool, not Quartus.

1) In Quartus, the connection is made by adding either the generated .qip file or the .qsys file itself to your Quartus project.  In a simulation tool, you would point to the working directory where all the files are located.  Platform Designer generates scripts for simulation tools to allow them to simulate a system, but it depends on your simulation tool.

2) scfifo would be the generic IP module name.  It probably references back to the Quartus and Platform Designer installation.

3) Avalon streaming and Avalon memory-mapped have opposite endianness (I forget which is big and which is little).  This must be doing the required bit (byte) swizzling.

4) (slave=agent) This is an agent interface that is accessed by a host in the system to read the data output and (optionally) status registers from the FIFO.  As such, a host would need to set the address to read in the FIFO (either the FIFO data output or a particular status register, like the FIFO full indicator for example).  If it's only one bit wide, then you probably aren't using the status interface (user guide says it's 3 bits wide when enabled).  It might leave the single bit input there for compatibility with the rest of the system

More info:

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/st-sink-to-mm-read-agent.html

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/status-interface.html

[Sijith]

Thank you very much for helping me. sorry I forgot to mention that my simulation tool is ModelSim.  Regarding the point 3,  is there any specific reason why we need bit swizzling here?. Is it something needed for the memory-mapped data transfer? If I manually modify

"assign avalonmm_data[7 : 0] = avalonst_data[31 : 24];
assign avalonmm_data[15 : 8] = avalonst_data[23 : 16];
assign avalonmm_data[23 : 16] = avalonst_data[15 : 8];
assign avalonmm_data[31 : 24] = avalonst_data[7 : 0];"

to have the same endianness, or it's not recommended?

I am curious that if I am streaming a bitstream data (say "100000100010001") to FIFO and then do a Memory Map read though the output port to a peripheral (say DDR4), then how this endianness mis-match will be corrected (I mean how the correct bit sequence "100000100010001" will be saved in the DDR4) 

Regarding the point 4, Yeh I am not using the status interface. I am just curious that if my host is some other IP, then the FIFO address will be set automatically by the "Assign Base-address"? or we have to do something manually? 

I have noticed that setting the "fifo_0_out_address"=0 in the simulation test bench (\FIFO_TEST\fifo_qsys\sim\fifo_qsys_tb.v) an output data that is having opposite endianness to that of "fifo_0_out_address"=1 . I have a hard time in understanding why this happening. Do you have any thought regarding this?

Thank you very much.

[sstrell]

No do not edit any files generated by PD. The whole point of the tool is for you to build your system how you want it and then let PD build the interconnect for you. There is no need for you to go in and look at or make changes to the generated code.

Read the user guide I linked to which is also linked to in PD. That explains how to use IP like the FIFO.

[ShengN_Intel]

Hi,

Check the document:

The FIFO core performs the endian conversion to conform to the output interface protocol.

If Enable packet data is turned off, read data repeatedly at address offset 0 to pop the data from the FIFO core. (At address offset 1 will not pop the data)

Thanks,

Best regards,

Sheng

[Sijith]

Thank you very much! 

I have noticed that setting the "fifo_0_out_address"=0 in the simulation test bench (\FIFO_TEST\fifo_qsys\sim\fifo_qsys_tb.v) an output data that is having opposite endianness to that of "fifo_0_out_address"=1 . I have a hard time in understanding why this happening. Do you have any thought regarding this?

The screenshot showing the simulation output for setting (simulated using the fifo_qsys_tb.v attached)

#1fifo_0_out_address=0

#10fifo_0_out_address=1

#10fifo_0_out_address=0

#10fifo_0_out_address=1

is attached Capture_modelsim1.PNG (please see the readdata and fifo_0_out_address signals in the modelsim wave output). I am confused why endian conversion in FIFO core is affected by the avalon mm input signal fifo_0_out_address ?

[ShengN_Intel · Accepted solution]

Hi,

When "fifo_0_out_address"=1, readdata take in the channel value but not having opposite endianness check image below:

As this time channel had been being assigned some value.

Check document details:

If the read is valid, that is, the FIFO core is not empty, both data and packet status information are popped from the FIFO core. The packet status information is obtained by reading at address offset 1. Reading from address offset 1 does not pop data from the FIFO core.

Thanks,

Best regards,

Sheng

[ShengN_Intel]

Hi,

Any further update or concern?

Thanks,

Best regards,

Sheng