Integrating OpenCL .cl files with RTL - Avalon required? Defining clocks, etc

[Altera_Forum]

Hi, 

 I couldn't find any documentation besides Library1 and Library2 examples on how to integrate RTL along with existing OpenCL code. I know that it is possible, and from Library2, an .xml file is used in order to relate the .vhd/.v module back to the OpenCL .cl file - but how is stuff like clocks specified? I took a look at Library2 as an example: There are a couple of input/output ports, but there are also many more Avalon ports. Is Avalon necessary to interface between the OpenCL and some RTL? I'm guessing it might be to deal with DMA issues etc. Additionally, I see in the example that clocks are defined but nowhere is clock freq specified.   In designing this file, would the process have been to design the RTL first in Quartus (i.e dropping the Avalon IP onto the design? Because the sumOfElements.v file has is fairly complicated with its Avalon interactions. which makes me think this .v wasn't written from first principles). Is there a document specifying how to interact between OpenCL and RTL?  Thanks for your time - please forgive my ignorance (usually I'm a Xilinx person...)  ap29

[Altera_Forum]

The official documentation for integrating RTL with OpenCL is in "Intel FPGA SDK for OpenCL Programming Guide, 11.1 OpenCL Library". Using Avalon is mandatory for this purpose. The RTL module will have the same clock as the OpenCL kernel, which does not need to be set by the user.

[Altera_Forum]

--- Quote Start ---  The official documentation for integrating RTL with OpenCL is in "Intel FPGA SDK for OpenCL Programming Guide, 11.1 OpenCL Library". Using Avalon is mandatory for this purpose. The RTL module will have the same clock as the OpenCL kernel, which does not need to be set by the user.  --- Quote End ---    Much thanks HRZ - apologies, I didn't realise it was in that documentation - I've read it already but must have missed that section somehow.