Hi., I am working with Arria 10 GX FPGA board and Intel Quartus Prime Pro Edition Design Software Version 21.4 for Windows. I am trying to integrate a my own verilog code to the FIFO IP provided. How I can do it in Quartus Prime Pro? (PS: I am new here). I was trying to follow https://www.youtube.com/watch?v=bwoyQ_RnaiA (How to begin a simple FPGA design). Exporting the verilog code to the symbol file (.bdf) and then connecting that to the .bdf file of the IP is a way I assume. I have watched this method of creating symbol file from a verilog file in the above youtube video (as shown in 25:15 and 31:56 playing time). But unfortunately in the Quartus Prime Pro version, the option File -> Create/Update ->Create Symbol file from Current File is grayed out.
I would like to know the way in which I can proceed? Or is there any similar functionality in Quartus Prime Pro that I can use to integrate a HDL stand alone code with an IP?
You can just Instantiating IP Cores in HDL.
The Quartus Pro does not support the Create Symbol Files for Current File. As design is getting bigger and complex, schematic design is not recommended. Please refer to the KDB below.
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