Intel Quatrus 22.1.2 , Qsys , DDR2 UniPHY IP generate error

[MAX10_nios2_terminal]

Hi all,

I have problem at Qsys for the generation of DDR2 IP. As i understand it is a common problem but there is no specific solution. I want to run an old project so i have regenerated and the problem occurs during Qsys generation. I am at Windows 11 so i have to use the latest free version of Quatrus which is the only one who can run on the specific OS. The problem that we get is the follow:

Error: s0: Error during execution of "{C:/intelfpga_lite/22.1std/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally

Error: s0: Execution of command "{C:/intelfpga_lite/22.1std/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed

Error: s0: /mnt/c/intelfpga_lite/22.1std/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../system_mem_if_ddr2_emif_0_s0_AC_ROM.hex -inst_rom ../system_mem_if_ddr2_emif_0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001001010011 -DAC_ROM_MR0_CALIB=0001001010011 -DAC_ROM_MR0_DLL_RESET=0001101010011 -DAC_ROM_MR1=0010001000100 -DAC_ROM_MR1_OCD_ENABLE=0011111000100 -DAC_ROM_MR2=0000010000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR= -DAC_ROM_MR0_DLL_RESET_MIRR= -DAC_ROM_MR1_MIRR= -DAC_ROM_MR2_MIRR= -DAC_ROM_MR3_MIRR= -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0

Error: s0: UniPHY Sequencer Microcode Compiler

Error: s0: Copyright (C) 2023 Intel Corporation. All rights reserved.

Error: s0: Info: Reading sequencer_mc/ac_rom.s ...

Error: s0: Info: Reading sequencer_mc/inst_rom.s ...

Error: s0: Info: Writing ../system_mem_if_ddr2_emif_0_s0_AC_ROM.hex ...

Error: s0: Info: Writing ../system_mem_if_ddr2_emif_0_s0_inst_ROM.hex ...

Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...

Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...

Error: s0: Info: Writing sequencer/sequencer_auto.h ...

Error: s0: Info: Writing sequencer/sequencer_auto.h ...

Error: s0: Info: Writing ../sequencer_auto_h.sv ...

Error: s0: Info: Microcode compilation successful

Error: s0: Makefile:27: recipe for target 'mc' failed

Error: s0: child process exited abnormally

Error: s0: Cannot find sequencer/sequencer.elf

Error: s0: An error occurred

while executing

"error "An error occurred""

(procedure "_error" line

invoked from within

"_error "Cannot find $seq_file""

("if" then script line 2)

invoked from within

"if {[file exists $seq_file] == 0} {

	\_error "Cannot find $seq\_file"

}"

(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)

invoked from within

"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""

invoked from within

"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"

("if" then script line 2)

invoked from within

"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {

	set calc\_mem\_size \[alt\_mem\_if::util::seq\_mem\_size::get\_max\_memory\_usage \[file join "sequenc..."

(procedure "generate_qsys_sequencer_sw" line 943)

invoked from within

"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."

invoked from within

"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."

("if" else script line 2)

invoked from within

"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {

	set seq\_mem\_size \[::alt\_mem\_if::util::qini::qini\_value alt\_mem\_if\_se..."

(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)

invoked from within

"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"

invoked from within

"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"

(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)

invoked from within

"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir SIM_VERILOG"

invoked from within

"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir SIM_VERILOG] {

	set file\_name \[file tail $generate..."

(procedure "generate_verilog_sim" line 7)

invoked from within

"generate_verilog_sim system_mem_if_ddr2_emif_0_s0"

----------------------------------------------------------------------------------------------------------------------------

Of course i have WSL enable, of course Nios 2 can run without problem. Also Ubuntu 18.04 and wsl version 1. I have tried many things from other posts at intel community. Some of them were to modify alt_mem_if\alt_mem_if_tcl_packages\gen\uniphy_gen.tcl and change the line : puts $fh "\t$qdir/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE" to the follow : puts $fh "\t$qdir/bin64/cygwin/bin/bash.exe $qdir/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE" . Also something similar from the follow link: https://community.intel.com/t5/Programmable-Devices/Quartus-18-1-Lite-Platform-Designer-DDR3-Controller-can-t-build/td-p/1339839 . But nothing seems to work. Does anybody had it before or maybe can think of a possible solution ?

Thank you very much !!

[sstrell]

So back up a bit.  Can you show your Platform Designer system and connections and parameterization of the IP?  This happens when you try to generate the a system or are you saying that you are just generating the IP and instantiating it in an upper-level design file?

[MAX10_nios2_terminal]

Hi,

Either when generating the whole system or just the specific module it shows the same error. Even if I make a simpler example with just nios , memory etc again the same . Also i want to add that yesterady i tried the new lite version 23.1 of quatrus and the same error occur at the generation of the DDR UniPHY module. 

[SyafieqS]

Perhaps you can share with me the design that able to reproduce the issue, ill replicate at my end to see whether this is a bug or something else

[SyafieqS]

Let me know if there is any update

[TomCarpenter]

For anyone with a similar issue with Quartus 22.1, this appears to be an incorrect assumption in the nios2_command_shell.sh script which causes it to fail to properly detect WSL2 on some (all? every one I've used it on) machines. This causes it to think the host OS is Linux not Windows.

The script assumes that WSL contains the text "Microsoft" (case sensitive) in /proc/version.  For WSL2 with Ubuntu 20.02 LTS, this is not the case, instead it contains:

Linux version 5.15.153.1-microsoft-standard-WSL2 (root@941d701f84f1) (gcc (GCC) 11.2.0, GNU ld (GNU Binutils) 2.37) #1 SMP Fri Mar <> 23:14:13 UTC 2024

Fortunately the fix is simple. Open the C:\intelFPGA\22.1std\nios2eds\nios2_command_shell.sh script file in a text editor (correct path based on your install directory, e.g. intelFPGA_lite), then scroll down to line 160.

Change:

if grep -q Microsoft /proc/version; then

to:

if grep -i -q Microsoft /proc/version; then

This will make the grep comparison case insensitive, allowing it to pick up the original "Microsoft", and also the lower case "microsoft" in the 5.15.153.1-microsoft-standard-WSL2 string.