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Intel Questa FPGA Starter Edition Error: ** Fatal: (vsim-160)

LFrin
New Contributor I
941 Views

Hello,

I have a problem simulating my design with Questa.

Tools: Quartus Pro 22.3, Questa FPGA Starter 2022.1

Hardware: Terasic HAN-Pilot-Platform, Arria 10 SOC (10AS066K3F40E2SG)

This is the manual i used to get an basic example running: Questa Quick Start for Quartus Pro

Then i tried to simulate my complexer design i use on my evaluationboard and i get this fatal error and i have no clue how to fix it:

 

** Fatal: (vsim-160) hps/hps/altera_arria10_interface_generator_140/sim/mgc_common_axi.sv(3198): Null foreign function pointer encountered when calling 'dvc_axi_initialise_SystemVerilog'

# Time: 0 fs Iteration: 0 Process: /test_bench/com_golden_top/com_hps/hps/fpga_interfaces/f2sdram0_data_inst/axi/#INITIAL#3219 File: hps/hps/altera_arria10_interface_generator_140/sim/mgc_common_axi.sv

 

It seems to have something to do with the HPS. Can someone help me fix this?

 

 

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6 Replies
IntelSupport
Community Manager
922 Views

From the error message, you may need to check the installation and configuration of the Interface Generator, verify that all necessary files are present and correctly referenced, and ensure that any required environment variables or settings are properly configured. Additionally, you may need to review the code that is calling the foreign function pointer (function:dvc_axi_initialise_SystemVerilog) in mgc_common_axi.sv to ensure that it is being used correctly and that all necessary parameters are being passed.


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IntelSupport
Community Manager
894 Views

May I know if there is any update from previous reply?


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LFrin
New Contributor I
875 Views

Hello,

No I have not made any progress yet. The source code that produces the error in Questa was automatically generated by Quartus and is not my code.

I have completely regenerated the HPS component again. Unfortunately the error still exists. I have no problems with the Component when i use it in the hardware, only when i try to simulate it.

The compilation works. But after calling elab_debug the task crashs with the above mentioned critical error.

Regards, LFrin

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IntelSupport
Community Manager
828 Views

I see you are using Pro edition, i assume you must have a Questa FPGA edition as well. Have you tried using the other simulation tool other than starter edition? Also, its not a good practice to ignore the simulation.

Or else, you can verify the real time functionality using signal tap, that would be another method as well


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LFrin
New Contributor I
803 Views

Hello,

Unfortunately, I'm only evaluating the pro edition right now. I don't have Questa FPGA at hand, only the starter edition. We will have to buy the pro version in the future, then I will test if it works with the other simulation tool.

 

I think i will ignore the simulation for now and try to verify the real time functionality with the evaluationboard i have.

 

Regards, LFrin

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IntelSupport
Community Manager
762 Views

Understood. With that I will put this to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey


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