Is Quartus Prime really support VHDL 2008?

BLee15 · ‎09-04-2018

According to "Intel Quartus Prime Support for VHDL 2008" (https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_list_2008_vhdl_support.htm), Quartus supports some subset of VHD 2008.

However, it seems that the implementation is not correct.

According to Section 9.2.3, result of STD_ULOGIC ?= STD_ULOGIC should STD_ULOGIC. However, the following code snippet failed to compile with error 10327: can't determine definition of operator ""?="" -- found 0 possible definitions

-- synthesis VHDL_INPUT_VERSION VHDL_2008
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity demo is
	port (
		a: in std_ulogic;
		b: in std_ulogic;
		r: out std_ulogic
	);
end;
 
architecture rtl of demo is
begin
	r <= a ?= b;
end;

Modifying type of r to boolean elimates error.

Moreover, in the VHDL-2008, STD_LOGIC_VECTOR is subtype of STD_ULOGIC_VECTOR, and STD_ULOGIC_VECTOR is one-dimensional array type whose element is std_ULOGIC. Therefore, STD_LOGIC_VECTOR ?= STD_LOGIC_VECTOR should be defined. However, the following snippet also failed with similar error:

-- synthesis VHDL_INPUT_VERSION VHDL_2008
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity demo is
	port (
		a: in std_logic_vector(3 downto 0);
		b: in std_logic_vector(3 downto 0);
		r: out boolean
	);
end;
 
architecture rtl of demo is
begin
	r <= a ?= b;
end;

Modifying type of a and b to std_ulogic_vector elimates error.

I'm using Quartus Prime Lite version 18.0.0

As I don't have Pro license, I also want to ask whether the Pro version can compile these code snippet without error.

Tricky · ‎09-04-2018

Quartus prime has very limited 2008 support that hasn't been updated for several years. But Pro version should have full support.

For your examples

1. Have you tried with std_logic rather than std_ulogic? With only basic support, this may be supported (but also may not be). It may have been included simply to support

If sl then

Where sl is a std_logic rather than Boolean.

2. You have the syntax wrong. Slv ?= Slv returns a std_logic, not a Boolean. Either change r to a std_logic (as vhdl 2008) or change code to use =

R <= (a =b);

As per vhdl '87

Modelsim has full 2008 support. It might be prudent to stick to 1993 style for synthesis code (because 2008 is only a minor help) and 2008 for test benches, where 2008 is very useful.

BLee15 · ‎09-04-2018

changing a, b, r to std_logic also returns error.
Only boolean <= STD_ULOGIC_VECTOR ?= STD_ULOGIC_VECTOR compiles without error; all of the following combination returns error:
1. STD_LOGIC <= STD_LOGIC_VECTOR ?= STD_LOGIC_VECTOR
2. STD_ULOGIC <= STD_LOGIC_VECTOR ?= STD_LOGIC_VECTOR
3. boolean <= STD_LOGIC_VECTOR ?= STD_LOGIC_VECTOR
4. STD_LOGIC <= STD_ULOGIC_VECTOR ?= STD_ULOGIC_VECTOR
5. STD_ULOGIC <= STD_ULOGIC_VECTOR ?= STD_ULOGIC_VECTOR