Is is gonna be very long propagation time for multi-bits mux?

Altera_Forum · ‎02-10-2011

I did a mux that take a 18-bit input and a 19-bit input and a 18 bit-output.

It seems that from the simulation, it takes really long time to make the change to the output everytime one of the inputs changes.

Below is the simulation results... I'm wondering this kind of gates will definitely affect

our maximum clock frequency... how could I do to avoid this?

Altera_Forum · ‎02-10-2011

Most substantial information is missing for a serious answer.

Do you show pin-to-pin delays? They have nothing to do with internal delays that count for maximum clock frequency. What's the involved device family? how to mux 19 bit to 18 bit, is it more than a simple multiplexer (a single LE per bit)?

Altera_Forum · ‎02-10-2011

Hi FvM,

Is this the pin to pin delay i should show？

And a question: what's the difference between pin-to-pin delay and internal delays? Why it doesn't affect fmax?

I used cyclone.

and my code:


module mux(d,o,mux_sel,mux_out);
input  d;
input  o;
input mux_sel;
output reg  mux_out;
always@(*)
  if(mux_sel)
    mux_out=o;
  else
    mux_out=d;
    
endmodule

Altera_Forum · ‎02-10-2011

Thanks for clarification. This is a simple mux involving one LE in combinational mode per bit. The delay caused by a single LE, as it would count between two registers is considerably below a nanosecond. Most of the delay in your test is caused by the I/O cells, particularly the output driver.

Generally, the available speed of the internal logic will be observed by the Quartus timing analysis. For a simple design, involving only a single system clock, you can try the Classical Timing Analyzer to get an idea. You will notice, that when the logic path between registers gets longer, the maximum achievable clock frequency will drop.

For asynchronous circuits as your above example no maximum clock frequency can be calculated unless registers come into play.

Altera_Forum · ‎02-10-2011

Thanks bro, this clears up everything.