Is there a plan to fix VHDL code of Cyclonev_atom? it contain plenty of errors.

[ARach7]

Cyclonev VHDL flavor gives elaboration error with VCS. They are justified.

Is there an ETA for  a fix ?​

%sed -n '6482,6599p;6599q'  /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclonev_atoms.vhd > t.vhd

%cat t.v

module tb();

cyclonev_termination cyclonev_termination ();

endmodule

%vlogan +v2k /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v t.v

%vhdlan t.vhd

%vcs tb

Error-[BADFORMALSPEC] Bad formal part specified

 Formal port 'SCANIN' in component 'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

 (t_2.vhd:26) cannot be found in module

 'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

 (/global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v:25).

 Please review section 4.3.2.2 (Association Lists) of the VHDL93 LRM for the

 rules of association lists.

Error-[BADFORMALSPEC] Bad formal part specified

 Formal port 'SCANOUT' in component 'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

 (t_2.vhd:26) cannot be found in module

 'CYCLONEV_TERMINATION_LOGIC_ENCRYPTED'

 (/global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v:25).

 Please review section 4.3.2.2 (Association Lists) of the VHDL93 LRM for the

 rules of association lists.

Error-[BADFORMALSPEC] Bad formal part specified

 Formal generic 'A_OCT_TEST_3' in component 'CYCLONEV_TERMINATION_ENCRYPTED'

 (t.vhd:46) cannot be found in module 'CYCLONEV_TERMINATION_ENCRYPTED'

 (/global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v:25).

 Please review section 4.3.2.2 (Association Lists) of the VHDL93 LRM for the

 rules of association lists.

Error-[ANALERR_SIZEMISMATCH1] Size mismatch

 Mismatch found between the actual named 'OTHERENSER', whose type size is 9,

 and the formal named 'OTHERENSER', whose type size is 10. Actual

 'OTHERENSER' is defined in COMPONENT named CYCLONEV_TERMINATION_ENCRYPTED in

 file t.vhd at line 71. Formal 'OTHERENSER' is defined in MODULE named

 CYCLONEV_TERMINATION_ENCRYPTED in file

 /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v

 at line 25.

[KhaiChein_Y_Intel]

Hi,

Can you provide a test case and steps to reproduce the error?

Thanks.

[ARach7]

Sure.

1.  Strip the definitions of entity   cyclonev_termination and of entity   cyclonev_termination_logic  from the full file:

         (Please change path of  $Quartus_ROOTDIR , to match your installation of quartus_18.0.0.614)

%sed -n '6482,6599p;6599q' /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclonev_atoms.vhd > stam.vhd

%sed -n '6421,6481p;6481q' /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclonev_atoms.vhd > stam2.vhd

2.Create this t.v  Verilog file

module tb_cyclonev_termination();

cyclonev_termination  cyclonev_termination ();

endmodule

module tb_cyclonev_termination_logic();

cyclonev_termination_logic cyclonev_termination_logic ();

endmodule

3.Run these VCS commands:

%vlogan t.v

%vhdlan stam.vhd sta2.vhd

%vcs tb_cyclonev_termination

You will get 4 errors of Error-[BADFORMALSPEC] Bad formal part specified, one error of Error-[ANALERR_SIZEMISMATCH1] Size mismatch, one error of Error-[ANL-PORTDI-ERR] Port direction mismatch

Now run this command

%vcs tb_cyclonev_termination_logic

You will get two errors of type Error-[BADFORMALSPEC] Bad formal part specified

[KhaiChein_Y_Intel]

Hi,

Please allow me some time to duplicate this.

Thanks.

[KhaiChein_Y_Intel]

Hi,

It seems like the sta2.vhd file is missing.

vhdlan stam.vhd sta2.vhd gives error below:

Parsing design file 'stam.vhd'

Parsing design file 'sta2.vhd'

Error: analysis Parsing vhdl-783

Source file sta2.vhd cannot be opened for reading.

May I request this file?

Thanks.

Best regards,

YY

[ARach7]

​File name is stam2.vhd. It is just a typo, sorry.

You got instructions how to create that file using this command:

%sed -n '6421,6481p;6481q' /global/snps_apps/quartus_18.0.0.614/quartus/eda/sim_lib/cyclonev_atoms.vhd > stam2.vhd

[KhaiChein_Y_Intel]

Hi,

I cannot reproduce the error. Running vcs tb_cyclonev_termination gives error below:

*** Using c compiler gcc instead of cc ...

             Chronologic VCS (TM)

   Version N-2017.12-SP2-4_Full64 -- Wed Jul 10 16:17:58 2019

        Copyright (c) 1991-2017 by Synopsys Inc.

             ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.

and may be used and disclosed only as authorized in a license agreement

controlling such use and disclosure.

Top Level Modules:

    tb_cyclonev_termination

Warning-[ELW_UNBOUND] Unbound component

 The component instantiation 

 '/\/tb_cyclonev_termination/cyclonev_termination\/INST' (file: 

 /folder/stam.vhd, line: 82) will 

 have no effect because component 'CYCLONEV_TERMINATION_ENCRYPTED' is 

 unbound. No entity definition for component 'CYCLONEV_TERMINATION_ENCRYPTED'

 can be found in the following libraries ( WORK ) referenced by the 

 architecture 'BEHAVIOR' of entity 'CYCLONEV_TERMINATION'.

 Please bind the component explicitly to an entity (architecture) pair, and 

 verify that the pair was analyzed successfully.

TimeScale is 1 s / 1 ns

Warning-[TFIPC] Too few instance port connections

t.v, 3

"cyclonev_termination cyclonev_termination();"

 The above instance has fewer port connections than the module definition.

 Please use '+lint=TFIPC-L' to print out detailed information of unconnected 

 ports.

Note-[SIMU-RESOLUTION] Simulation time resolution

 Simulation time resolution is 1 NS

Starting vcs inline pass...

2 modules and 0 UDP read.

However, due to incremental compilation, no re-compilation is necessary.

make: Warning: File `vh/sc_filelist' has modification time 9.5 s in the future

make[1]: Warning: File `vh/sc_filelist' has modification time 9.5 s in the future

rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so

make[1]: warning: Clock skew detected. Your build may be incomplete.

make[1]: Warning: File `vh/sc_filelist' has modification time 9.5 s in the future

ld -shared -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o 

rm -f _csrc0.so

make[1]: warning: Clock skew detected. Your build may be incomplete.

if [ -x ../simv ]; then chmod -x ../simv; fi

g++ -o ../simv  -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic -Wl,-E -Wl,-rpath=/tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib -L/tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib  _1668_archive_1.so _prev_archive_1.so _csrc0.so SIM_l.o _csrc0.so   rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o    linux64_scvhdl_0.so vh/scscomm.o vh/scsFilelist.o  -lzerosoft_rt_stubs -lerrorinf -lsnpsmalloc -lvfs  -lvirsim -lvcsnew /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/vcs_main.o -lvcsmx -lreader_common /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/libBA.a -lsimprofile -luclinative /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/vcs_tls.o  -Wl,-whole-archive -Wl,-no-whole-archive      /tools/vcsmx/N-2017.12-SP2-4/linux64/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl 

../simv up to date

make: warning: Clock skew detected. Your build may be incomplete.

CPU time: .385 seconds to compile + .014 seconds to elab + .231 seconds to link

Thanks.

Best regards,

YY

[KhaiChein_Y_Intel]

Hi,

Are you simulating some module created in the Intel Quartus Prime software? User cannot compile the file directly in the software.

Thanks.

[ARach7]

My bad, the copy-paste from shell to this web interface dropped following command:

%vlogan +v2k $QUARTUS_ROOTDIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v

[ARach7]

​Please reply if you are now able to get the errors described above.

[KhaiChein_Y_Intel]

Hi,

User cannot compile the simulation libraries by extracting part of the HDL as some of the files will be miss out.Below is the recommended ways to run the simulation:

1. Specify the EDA simulator and executable path in the Intel Quartus Prime software
2. Compile simulation model libraries using one of the following methods:
   1. Nativelink RTL simulation to compile required design files, simulation models and run the simulator.
   2. Use Quartus Simulation Library Compiler to automatically compile all required simulation models in your design.
3. Modify the simlib_comp.vcs file to specify your design and testbench files
4. Run the VCS simulator.

It is recommended to use the Simulation Library Compiler to compile the required simulation model instead of compiling one by one.

Thanks.

[ARach7]

I am afraid that the last reply not answer the problem.  

You have VHDL file with Verilog instances, that mismatch in various aspects (ports, etc).

It is not a matter of flow , it is a pure design bug.

I think I am wasting my time with this kind of support.

[KhaiChein_Y_Intel]

Hi,

I actually tried to compile all the simulation library files without stripping it. The error mentioned did not occur. I was thinking if we miss out some of the important files that cause this error. This is the reason why I suggest to compile/simulate using the proper flow above and see if the same error occurs. Then we can check one by one to figure out what is the root cause of this.

Thanks for understanding.

Thanks.

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