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It is strange to me that the verilog program behave differently when I turn a register variable into an output register variable.

GGan4
Beginner
789 Views

I write a finite state machine module using verilog. The state variable is a 2-bit register named STATE. It is strange to me that the program operates correctly only when I set STATE as an output. Is there anyone knows the reason for it, or the difference between whether I set a register variable as output or not?

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ak6dn
Valued Contributor III
91 Views

You have not provided enough information for anyone to comment in a reasonable fashion. What behaves differently, a simulator (which one) or a compiled FPGA? What is the difference? What is the context in which that register variable is used? It is just internal to a module instance, or is it actually an output of a module feeding other signals, that may feedback into an input into the module / state machine?

 

You need to provide snippets of actual code, what environment you are using, and what is the failed behavior vs expected behavior.

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